| Line 74... |
Line 74... |
-- base adress for transfer
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-- base adress for transfer
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opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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opb_rx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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opb_rx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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opb_rx_dma_done : out std_logic;
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opb_rx_dma_done : out std_logic;
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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opb_abort_flg : out std_logic);
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opb_abort_flg : out std_logic;
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opb_m_last_block : out std_logic);
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end opb_m_if;
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end opb_m_if;
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architecture behavior of opb_m_if is
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architecture behavior of opb_m_if is
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|
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type state_t is (idle,
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type state_t is (idle,
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| Line 108... |
Line 109... |
signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal opb_rx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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signal opb_rx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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signal opb_rx_dma_done_int : std_logic;
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signal opb_rx_dma_done_int : std_logic;
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begin -- behavior
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begin -- behavior
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--* convert M_DBus_big_end to little endian
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--* convert M_DBus_big_end to little endian
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process(M_DBus_big_end)
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process(M_DBus_big_end)
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begin
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begin
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| Line 175... |
Line 175... |
M_select_int <= '0';
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M_select_int <= '0';
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M_seqAddr <= '0';
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M_seqAddr <= '0';
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opb_tx_dma_done_int <= '0';
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opb_tx_dma_done_int <= '0';
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opb_rx_dma_done_int <= '0';
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opb_rx_dma_done_int <= '0';
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opb_abort_flg <= '0';
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opb_abort_flg <= '0';
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opb_m_last_block <= '0';
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opb_tx_dma_num_int <= (others => '0');
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opb_rx_dma_num_int <= (others => '0');
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elsif rising_edge(OPB_Clk) then
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elsif rising_edge(OPB_Clk) then
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case state is
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case state is
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when idle =>
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when idle =>
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opb_abort_flg <= '0';
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opb_abort_flg <= '0';
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opb_tx_dma_en <= opb_tx_dma_ctl(0);
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opb_tx_dma_en <= opb_tx_dma_ctl(0);
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| Line 219... |
Line 222... |
M_seqAddr <= '1';
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M_seqAddr <= '1';
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M_BE <= "1111";
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M_BE <= "1111";
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if (read_transfer) then
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if (read_transfer) then
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-- read
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-- read
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M_RNW <= '1';
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M_RNW <= '1';
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if (conv_integer(opb_tx_dma_num_int) = 0) then
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opb_m_last_block <= '1';
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end if;
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state <= transfer_read;
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state <= transfer_read;
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else
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else
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-- write
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-- write
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M_RNW <= '0';
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M_RNW <= '0';
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if (conv_integer(opb_rx_dma_num_int) = 0) then
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opb_m_last_block <= '1';
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end if;
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state <= transfer_write;
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state <= transfer_write;
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end if;
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end if;
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else
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else
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state <= wait_grant;
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state <= wait_grant;
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end if;
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end if;
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| Line 244... |
Line 253... |
M_RNW <= '0';
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M_RNW <= '0';
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M_select_int <= '0';
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M_select_int <= '0';
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M_BE <= (others => '0');
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M_BE <= (others => '0');
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if (conv_integer(opb_tx_dma_num_int) = 0) then
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if (conv_integer(opb_tx_dma_num_int) = 0) then
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opb_tx_dma_done_int <= '1';
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opb_tx_dma_done_int <= '1';
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opb_m_last_block <= '0';
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else
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else
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opb_tx_dma_num_int <= opb_tx_dma_num_int-1;
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opb_tx_dma_num_int <= opb_tx_dma_num_int-1;
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end if;
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end if;
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state <= done;
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state <= done;
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end if;
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end if;
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| Line 277... |
Line 287... |
M_RNW <= '0';
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M_RNW <= '0';
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M_select_int <= '0';
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M_select_int <= '0';
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M_BE <= (others => '0');
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M_BE <= (others => '0');
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if (conv_integer(opb_rx_dma_num_int) = 0) then
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if (conv_integer(opb_rx_dma_num_int) = 0) then
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opb_rx_dma_done_int <= '1';
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opb_rx_dma_done_int <= '1';
|
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opb_m_last_block <= '0';
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else
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else
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opb_rx_dma_num_int <= opb_rx_dma_num_int-1;
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opb_rx_dma_num_int <= opb_rx_dma_num_int-1;
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end if;
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end if;
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state <= done;
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state <= done;
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end if;
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end if;
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