OpenCores
URL https://opencores.org/ocsvn/spi_slave/spi_slave/trunk

Subversion Repositories spi_slave

[/] [spi_slave/] [trunk/] [pcore/] [opb_spi_slave_v1_00_a/] [hdl/] [vhdl/] [opb_spi_slave.vhd] - Diff between revs 16 and 23

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 16 Rev 23
Line 40... Line 40... 
    C_SR_WIDTH        : integer              := 8;
 
    C_SR_WIDTH        : integer              := 8;
 
    C_MSB_FIRST       : boolean              := true;
 
    C_MSB_FIRST       : boolean              := true;
 
    C_CPOL            : integer range 0 to 1 := 0;
 
    C_CPOL            : integer range 0 to 1 := 0;
 
    C_PHA             : integer range 0 to 1 := 0;
 
    C_PHA             : integer range 0 to 1 := 0;
 
    C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 5;  -- depth 32
 
    C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 5;  -- depth 32
 
    C_DMA_EN          : boolean              := false);
 
    C_DMA_EN          : boolean              := false;
 
 
 
    C_CRC_EN          : boolean              := false);
 
 
 
 
 
  port (
 
  port (
 
    -- OPB signals (Slave Side)
 
    -- OPB signals (Slave Side)
 
    OPB_ABus    : in  std_logic_vector(0 to C_OPB_AWIDTH-1);
 
    OPB_ABus    : in  std_logic_vector(0 to C_OPB_AWIDTH-1);
 
    OPB_BE      : in  std_logic_vector(0 to C_OPB_DWIDTH/8-1);
 
    OPB_BE      : in  std_logic_vector(0 to C_OPB_DWIDTH/8-1);
Line 98... Line 99... 
      C_OPB_AWIDTH      : integer;
 
      C_OPB_AWIDTH      : integer;
 
      C_OPB_DWIDTH      : integer;
 
      C_OPB_DWIDTH      : integer;
 
      C_FAMILY          : string;
 
      C_FAMILY          : string;
 
      C_SR_WIDTH        : integer;
 
      C_SR_WIDTH        : integer;
 
      C_FIFO_SIZE_WIDTH : integer;
 
      C_FIFO_SIZE_WIDTH : integer;
 
      C_DMA_EN          : boolean);
 
      C_DMA_EN          : boolean;
 
 
 
      C_CRC_EN          : boolean);
 
    port (
 
    port (
 
      OPB_ABus        : in  std_logic_vector(0 to C_OPB_AWIDTH-1);
 
      OPB_ABus        : in  std_logic_vector(0 to C_OPB_AWIDTH-1);
 
      OPB_BE          : in  std_logic_vector(0 to C_OPB_DWIDTH/8-1);
 
      OPB_BE          : in  std_logic_vector(0 to C_OPB_DWIDTH/8-1);
 
      OPB_Clk         : in  std_logic;
 
      OPB_Clk         : in  std_logic;
 
      OPB_DBus        : in  std_logic_vector(0 to C_OPB_DWIDTH-1);
 
      OPB_DBus        : in  std_logic_vector(0 to C_OPB_DWIDTH-1);
Line 130... Line 132... 
      opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);
 
      opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);
 
      opb_tx_dma_ctl  : out std_logic_vector(0 downto 0);
 
      opb_tx_dma_ctl  : out std_logic_vector(0 downto 0);
 
      opb_tx_dma_num  : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
 
      opb_tx_dma_num  : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
 
      opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);
 
      opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);
 
      opb_rx_dma_ctl  : out std_logic_vector(0 downto 0);
 
      opb_rx_dma_ctl  : out std_logic_vector(0 downto 0);
 
      opb_rx_dma_num  : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0));
 
      opb_rx_dma_num   : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
 
 
 
      opb_rx_crc_value : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
 
 
 
      opb_tx_crc_value : in  std_logic_vector(C_SR_WIDTH-1 downto 0));
 
 
 
 
 
  end component;
 
  end component;
 
 
 
 
 
 
 
 
 
  component opb_m_if
 
  component opb_m_if
 
    generic (
 
    generic (
Line 178... Line 183... 
      opb_m_rx_data   : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
 
      opb_m_rx_data   : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
 
      opb_rx_dma_ctl  : in  std_logic_vector(0 downto 0);
 
      opb_rx_dma_ctl  : in  std_logic_vector(0 downto 0);
 
      opb_rx_dma_addr : in  std_logic_vector(C_OPB_DWIDTH-1 downto 0);
 
      opb_rx_dma_addr : in  std_logic_vector(C_OPB_DWIDTH-1 downto 0);
 
      opb_rx_dma_num  : in  std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
 
      opb_rx_dma_num  : in  std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
 
      opb_rx_dma_done : out std_logic;
 
      opb_rx_dma_done : out std_logic;
 
      opb_abort_flg   : out std_logic);
 
      opb_abort_flg    : out std_logic;
 
 
 
      opb_m_last_block : out std_logic);
 
  end component;
 
  end component;
 
 
 
 
 
  component shift_register
 
  component shift_register
 
    generic (
 
    generic (
 
      C_SR_WIDTH  : integer;
 
      C_SR_WIDTH  : integer;
Line 239... Line 245... 
      opb_ier      : in  std_logic;
 
      opb_ier      : in  std_logic;
 
      opb_isr      : out std_logic;
 
      opb_isr      : out std_logic;
 
      opb_isr_clr  : in  std_logic);
 
      opb_isr_clr  : in  std_logic);
 
  end component;
 
  end component;
 
 
 
 
 
 
 
  component crc_core
 
 
 
    generic (
 
 
 
      C_SR_WIDTH : integer);
 
 
 
    port (
 
 
 
      rst              : in  std_logic;
 
 
 
      opb_clk          : in  std_logic;
 
 
 
      crc_en           : in  std_logic;
 
 
 
      crc_clr          : in  std_logic;
 
 
 
      opb_m_last_block : in  std_logic;
 
 
 
      fifo_rx_en       : in  std_logic;
 
 
 
      fifo_rx_data     : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
 
 
 
      opb_rx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0);
 
 
 
      fifo_tx_en       : in  std_logic;
 
 
 
      fifo_tx_data     : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
 
 
 
      tx_crc_insert    : out std_logic;
 
 
 
      opb_tx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0));
 
 
 
  end component;
 
 
 
 
 
-- opb_if
 
-- opb_if
 
  signal opb_ctl_reg : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);
 
  signal opb_ctl_reg : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);
 
 
 
 
 
  signal opb_s_tx_en   : std_logic;
 
  signal opb_s_tx_en   : std_logic;
 
  signal opb_s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  signal opb_s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
Line 257... Line 281... 
  signal opb_tx_dma_num  : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
 
  signal opb_tx_dma_num  : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
 
  signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
 
  signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
 
  signal opb_rx_dma_ctl  : std_logic_vector(0 downto 0);
 
  signal opb_rx_dma_ctl  : std_logic_vector(0 downto 0);
 
  signal opb_rx_dma_num  : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
 
  signal opb_rx_dma_num  : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
 
 
 
 
 
 
 
  signal opb_rx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
 
 
  signal opb_tx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
 
 
 
 
  -- opb_m_if
 
  -- opb_m_if
 
  signal opb_m_tx_en   : std_logic;
 
  signal opb_m_tx_en   : std_logic;
 
  signal opb_m_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  signal opb_m_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  signal opb_m_rx_en   : std_logic;
 
  signal opb_m_rx_en   : std_logic;
 
  signal opb_m_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  signal opb_m_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  signal opb_abort_flg : std_logic;
 
  signal opb_abort_flg : std_logic;
 
 
 
  signal opb_m_last_block : std_logic;
 
 
 
 
 
-- shift_register
 
-- shift_register
 
  signal sr_tx_clk  : std_logic;
 
  signal sr_tx_clk  : std_logic;
 
  signal sr_tx_en   : std_logic;
 
  signal sr_tx_en   : std_logic;
 
  signal sr_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  signal sr_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
Line 291... Line 319... 
  signal fifo_tx_en   : std_logic;
 
  signal fifo_tx_en   : std_logic;
 
  signal fifo_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  signal fifo_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  signal fifo_rx_en   : std_logic;
 
  signal fifo_rx_en   : std_logic;
 
  signal fifo_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  signal fifo_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
 
 
 
 
 
 
  -- rx crc_core
 
 
 
  signal crc_clr       : std_logic;
 
 
 
  signal crc_en        : std_logic;
 
 
 
  signal tx_crc_insert : std_logic;
 
 
 
 
 
begin  -- behavior
 
begin  -- behavior
 
 
 
 
 
  --* 
  --* 
  virtex4_slk_buf : if C_FAMILY = "virtex4" generate
 
  virtex4_slk_buf : if C_FAMILY = "virtex4" generate
 
    --* If C_FAMILY=Virtex-4 use "IBUF"
 
    --* If C_FAMILY=Virtex-4 use "IBUF"
Line 328... Line 361... 
      C_OPB_AWIDTH      => C_OPB_AWIDTH,
 
      C_OPB_AWIDTH      => C_OPB_AWIDTH,
 
      C_OPB_DWIDTH      => C_OPB_DWIDTH,
 
      C_OPB_DWIDTH      => C_OPB_DWIDTH,
 
      C_FAMILY          => C_FAMILY,
 
      C_FAMILY          => C_FAMILY,
 
      C_SR_WIDTH        => C_SR_WIDTH,
 
      C_SR_WIDTH        => C_SR_WIDTH,
 
      C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH,
 
      C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH,
 
      C_DMA_EN          => C_DMA_EN)
 
      C_DMA_EN          => C_DMA_EN,
 
 
 
      C_CRC_EN          => C_CRC_EN)
 
    port map (
 
    port map (
 
      OPB_ABus        => OPB_ABus,
 
      OPB_ABus        => OPB_ABus,
 
      OPB_BE          => OPB_BE,
 
      OPB_BE          => OPB_BE,
 
      OPB_Clk         => OPB_Clk,
 
      OPB_Clk         => OPB_Clk,
 
      OPB_DBus        => OPB_DBus,
 
      OPB_DBus        => OPB_DBus,
Line 360... Line 394... 
      opb_tx_dma_addr => opb_tx_dma_addr,
 
      opb_tx_dma_addr => opb_tx_dma_addr,
 
      opb_tx_dma_ctl  => opb_tx_dma_ctl,
 
      opb_tx_dma_ctl  => opb_tx_dma_ctl,
 
      opb_tx_dma_num  => opb_tx_dma_num,
 
      opb_tx_dma_num  => opb_tx_dma_num,
 
      opb_rx_dma_addr => opb_rx_dma_addr,
 
      opb_rx_dma_addr => opb_rx_dma_addr,
 
      opb_rx_dma_ctl  => opb_rx_dma_ctl,
 
      opb_rx_dma_ctl  => opb_rx_dma_ctl,
 
      opb_rx_dma_num  => opb_rx_dma_num);
 
      opb_rx_dma_num   => opb_rx_dma_num,
 
 
 
      opb_rx_crc_value => opb_rx_crc_value,
 
 
 
      opb_tx_crc_value => opb_tx_crc_value);
 
 
 
 
 
  --* OPB-Master-Interface
 
  --* OPB-Master-Interface
 
  --*
 
  --*
 
  --* (DMA Read/Write Transfers to TX/RX-FIFO)
 
  --* (DMA Read/Write Transfers to TX/RX-FIFO)
 
 
 
 
Line 411... Line 447... 
        opb_m_rx_data   => opb_m_rx_data,
 
        opb_m_rx_data   => opb_m_rx_data,
 
        opb_rx_dma_ctl  => opb_rx_dma_ctl,
 
        opb_rx_dma_ctl  => opb_rx_dma_ctl,
 
        opb_rx_dma_addr => opb_rx_dma_addr,
 
        opb_rx_dma_addr => opb_rx_dma_addr,
 
        opb_rx_dma_num  => opb_rx_dma_num,
 
        opb_rx_dma_num  => opb_rx_dma_num,
 
        opb_rx_dma_done => opb_fifo_flg(14),
 
        opb_rx_dma_done => opb_fifo_flg(14),
 
        opb_abort_flg   => opb_abort_flg);
 
        opb_abort_flg    => opb_abort_flg,
 
 
 
        opb_m_last_block => opb_m_last_block);
 
  end generate dma_enable;
 
  end generate dma_enable;
 
 
 
 
 
  dma_disable : if (C_DMA_EN = false) generate
 
  dma_disable : if (C_DMA_EN = false) generate
 
    M_request        <= '0';
 
    M_request        <= '0';
 
    M_busLock        <= '0';
 
    M_busLock        <= '0';
Line 482... Line 519... 
      prog_empty        => opb_fifo_flg(3),
 
      prog_empty        => opb_fifo_flg(3),
 
      empty             => opb_fifo_flg(4),
 
      empty             => opb_fifo_flg(4),
 
      underflow         => opb_fifo_flg(5));
 
      underflow         => opb_fifo_flg(5));
 
 
 
 
 
  fifo_tx_en   <= opb_s_tx_en or opb_m_tx_en;
 
  fifo_tx_en   <= opb_s_tx_en or opb_m_tx_en;
 
  fifo_tx_data <= opb_m_tx_data when (opb_tx_dma_ctl(0) = '1') else
 
  fifo_tx_data <= opb_tx_crc_value when (C_CRC_EN and tx_crc_insert = '1') else
 
 
 
                  opb_m_tx_data when (opb_tx_dma_ctl(0) = '1') else
 
                  opb_s_tx_data;
 
                  opb_s_tx_data;
 
 
 
 
 
  --* Receive FIFO
 
  --* Receive FIFO
 
  rx_fifo_1 : fifo
 
  rx_fifo_1 : fifo
 
    generic map (
 
    generic map (
Line 566... Line 604... 
  -- assert irq if one Interupt Status bit set
 
  -- assert irq if one Interupt Status bit set
 
  opb_irq <= '1' when (conv_integer(opb_isr) /= 0 and opb_dgie = '1') else
 
  opb_irq <= '1' when (conv_integer(opb_isr) /= 0 and opb_dgie = '1') else
 
             '0';
 
             '0';
 
 
 
 
 
 
 
 
 
 
 
  -----------------------------------------------------------------------------
 
 
 
 
 
 
 
  -- clear start_value at power up and soft_reset
 
 
 
  crc_en  <= opb_ctl_reg(C_OPB_CTL_REG_CRC_EN);
 
 
 
  crc_clr <= opb_ctl_reg(C_OPB_CTL_REG_CRC_CLR) or rst;
 
 
 
 
 
 
 
  crc_gen : if (C_CRC_EN) generate
 
 
 
    crc_core_1 : crc_core
 
 
 
      generic map (
 
 
 
        C_SR_WIDTH => C_SR_WIDTH)
 
 
 
      port map (
 
 
 
        rst              => rst,
 
 
 
        opb_clk          => opb_clk,
 
 
 
        crc_en           => crc_en,
 
 
 
        crc_clr          => crc_clr,
 
 
 
        opb_m_last_block => opb_m_last_block,
 
 
 
        fifo_rx_en       => fifo_rx_en,
 
 
 
        fifo_rx_data     => fifo_rx_data,
 
 
 
        opb_rx_crc_value => opb_rx_crc_value,
 
 
 
        fifo_tx_en       => fifo_tx_en,
 
 
 
        fifo_tx_data     => fifo_tx_data,
 
 
 
        tx_crc_insert    => tx_crc_insert,
 
 
 
        opb_tx_crc_value => opb_tx_crc_value);
 
 
 
  end generate crc_gen;
 
 
 
 
 
 
 
 
 
end behavior;
 
end behavior;
 
 
 
 
 
 No newline at end of file
 
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.