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Line 15... |
--* @version: 1.1
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--* @version: 1.1
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--* @date: 2007-11-11
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--* @date: 2007-11-11
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--/
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--/
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-- Version 1.0 Initial Release
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-- Version 1.0 Initial Release
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-- Version 1.1 rx_cnt/tx_cnt only increment if < C_SR_WIDTH
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-- Version 1.1 rx_cnt/tx_cnt only increment if < C_SR_WIDTH
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-- Version 1.2 removed delays for simulation
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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| Line 82... |
Line 83... |
sclk_int <= sclk when (C_PHA = 0 and C_CPOL = 0) else
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sclk_int <= sclk when (C_PHA = 0 and C_CPOL = 0) else
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sclk when (C_PHA = 1 and C_CPOL = 1) else
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sclk when (C_PHA = 1 and C_CPOL = 1) else
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not sclk;
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not sclk;
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sr_rx_en <= transport sr_rx_en_int after 1 ns;
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sr_rx_en <= sr_rx_en_int;
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sr_tx_en <= transport sr_tx_en_int after 1 ns;
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sr_tx_en <= sr_tx_en_int;
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--* reorder received bits if not "MSB_First"
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--* reorder received bits if not "MSB_First"
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reorder_rx_bits : process(sr_rx_data_int)
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reorder_rx_bits : process(sr_rx_data_int)
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begin
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begin
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for i in 0 to C_SR_WIDTH-1 loop
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for i in 0 to C_SR_WIDTH-1 loop
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if C_MSB_FIRST then
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if C_MSB_FIRST then
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sr_rx_data(i) <= transport sr_rx_data_int(i) after 1 ns;
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sr_rx_data(i) <= sr_rx_data_int(i);
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else
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else
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sr_rx_data(C_SR_WIDTH-1-i) <= transport sr_rx_data_int(i)after 1 ns;
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sr_rx_data(C_SR_WIDTH-1-i) <= sr_rx_data_int(i);
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end if;
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end if;
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end loop; -- i
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end loop; -- i
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end process reorder_rx_bits;
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end process reorder_rx_bits;
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--* reorder transmit bits if not "MSB_First"
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--* reorder transmit bits if not "MSB_First"
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