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// RTL program for SPI GPIO -- shift 16 bit register
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// SPI GPIO IP Core ////
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//// ////
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//// This file is part of the spigpio project ////
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//// http://www.opencores.org/project,spislave ////
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//// ////
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//// Description ////
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//// Implementation of spislave IP core according to ////
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//// spigpio IP core specification document. ////
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//// ////
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//// To Do: ////
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//// - ////
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//// ////
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//// Author(s): ////
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//// - Sivakumar.B , email: siva@zilogic.com ////
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//// email: siva12@opencores.org ////
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//// Engineer Zilogic systems,chennai. www.zilogic.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 Zilogic Systems and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// RTL program for SPI SLAVE -- shift 8 bit register ////
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`define P0_OP 7'b0000000 //0x00
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`define P0_OP 7'b0000000 //0x00
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`define P1_OP 7'b0000001 //0x01
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`define P1_OP 7'b0000001 //0x01
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`define P2_OP 7'b0000010 //0x02
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`define P2_OP 7'b0000010 //0x02
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`define P3_OP 7'b0000011 //0x03
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`define P3_OP 7'b0000011 //0x03
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