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[/] [spimaster/] [trunk/] [RTL/] [spiMaster_defines.v] - Diff between revs 2 and 3
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// Version 1.0 - 3rd June 2008. Fixed synchronisation issue between busClk and
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// Version 1.0 - 3rd June 2008. Fixed synchronisation issue between busClk and
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// spiSysClk. Fixed bug in bus accessible reset. Changed names of
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// spiSysClk. Fixed bug in bus accessible reset. Changed names of
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// fifo related modules to avoid conflict with other IP cores.
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// fifo related modules to avoid conflict with other IP cores.
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// Version 1.1 - 23rd August 2008. Modified reset synchronisation. Fixed bug
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// Version 1.1 - 23rd August 2008. Modified reset synchronisation. Fixed bug
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// in wb_ack. Fixed file headers, and added description
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// in wb_ack. Fixed file headers, and added description
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// Version 1.2 - 25th October 2008. Modified readWriteSPIWireData to clock data
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// from the SPI bus on the rising edge of SCLK. This increases the
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// tsetup timing margin when reading SPI data. It turns out that the timing
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// was marginal for some SD cards when using a 24Mhz SPI clock.
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// Problem was exacerbated by the fact that the design prevents the
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// final SPI interface Flipflops being pushed into the IO blocks.
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`define SPI_MASTER_VERSION_NUM 8'h11
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`define SPI_MASTER_VERSION_NUM 8'h12
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`define SPI_SYS_CLK_48MHZ
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`define SPI_SYS_CLK_48MHZ
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//`define SPI_SYS_CLK_30MHZ
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//`define SPI_SYS_CLK_30MHZ
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//memoryMap
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//memoryMap
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`define CTRL_STS_REG_BASE 8'h00
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`define CTRL_STS_REG_BASE 8'h00
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