| Line 18... |
Line 18... |
|
|
module sound1942;
|
module sound1942;
|
// inputs to Z80
|
// inputs to Z80
|
reg reset_n, clk, int_n, sound_clk;
|
reg reset_n, clk, int_n, sound_clk;
|
parameter dump_text = 1; // set to 1 to dump data to use log2wav later
|
parameter dump_text = 1; // set to 1 to dump data to use log2wav later
|
|
parameter pwm_sound=1;
|
|
|
initial begin
|
initial begin
|
/* $dumpfile("dump.lxt");
|
/* $dumpfile("dump.lxt");
|
$dumpvars(1,pwm0);
|
$dumpvars(1,pwm0);
|
$dumpvars(1,pwm1);*/
|
$dumpvars(1,pwm1);*/
|
| Line 31... |
Line 32... |
// $shm_probe( sound1942, "ACTFS" );
|
// $shm_probe( sound1942, "ACTFS" );
|
reset_n=0;
|
reset_n=0;
|
#1500 reset_n=1;
|
#1500 reset_n=1;
|
$display("1942 START");
|
$display("1942 START");
|
// change finish time depending on song
|
// change finish time depending on song
|
//#0.1e9 $finish;
|
//#3000 $finish;
|
#7e9 $finish;
|
#6e9 $finish;
|
end
|
end
|
|
|
always begin // main clock
|
always begin // main clock
|
clk=0;
|
clk=0;
|
forever clk = #167 ~clk;
|
forever clk = #167 ~clk;
|
| Line 62... |
Line 63... |
wire [3:0] ay0_a, ay0_b, ay0_c, ay1_a, ay1_b, ay1_c;
|
wire [3:0] ay0_a, ay0_b, ay0_c, ay1_a, ay1_b, ay1_c;
|
computer_1942 #(0) game( .clk(clk), .sound_clk(sound_clk),
|
computer_1942 #(0) game( .clk(clk), .sound_clk(sound_clk),
|
.int_n(int_n), .reset_n(reset_n),
|
.int_n(int_n), .reset_n(reset_n),
|
.ay0_a(ay0_a), .ay0_b(ay0_b), .ay0_c(ay0_c),
|
.ay0_a(ay0_a), .ay0_b(ay0_b), .ay0_c(ay0_c),
|
.ay1_a(ay1_a), .ay1_b(ay1_b), .ay1_c(ay1_c) );
|
.ay1_a(ay1_a), .ay1_b(ay1_b), .ay1_c(ay1_c) );
|
// sound amplifier:
|
|
/*
|
if ( pwm_sound ) begin // PWM OUTPUT
|
wire [15:0] amp0_y, amp1_y;
|
|
SQM_AMP amp0( .A(ay0_a), .B(ay0_b), .C(ay0_c), .Y( amp0_y ));
|
|
SQM_AMP amp1( .A(ay1_a), .B(ay1_b), .C(ay1_c), .Y( amp1_y ));
|
|
always #22676 $display("%d", amp0_y+amp1_y ); // 44.1kHz sample
|
|
*/
|
|
reg vhf_clk;
|
reg vhf_clk;
|
always begin
|
always begin
|
vhf_clk=0;
|
vhf_clk=0;
|
forever begin
|
forever begin
|
if( vhf_clk && dump_text ) begin
|
if( vhf_clk && dump_text ) begin
|
| Line 88... |
Line 84... |
SQM_PWM_1 c0pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay0_c), .pwm(pwm0_c) );
|
SQM_PWM_1 c0pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay0_c), .pwm(pwm0_c) );
|
|
|
SQM_PWM_1 a1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_a), .pwm(pwm1_a) );
|
SQM_PWM_1 a1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_a), .pwm(pwm1_a) );
|
SQM_PWM_1 b1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_b), .pwm(pwm1_b) );
|
SQM_PWM_1 b1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_b), .pwm(pwm1_b) );
|
SQM_PWM_1 c1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_c), .pwm(pwm1_c) );
|
SQM_PWM_1 c1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_c), .pwm(pwm1_c) );
|
|
end
|
|
else begin // LINEAR OUTPUT
|
|
wire [15:0] amp0_y, amp1_y;
|
|
SQM_AMP amp0( .A(ay0_a), .B(ay0_b), .C(ay0_c), .Y( amp0_y ));
|
|
SQM_AMP amp1( .A(ay1_a), .B(ay1_b), .C(ay1_c), .Y( amp1_y ));
|
|
always #22676 begin // 44.1kHz sample
|
|
$display("%d", amp0_y*10 );
|
|
$display("%d", amp1_y *10);
|
|
end
|
|
end
|
endmodule
|
endmodule
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
