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module sound1942;
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module sound1942;
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// inputs to Z80
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// inputs to Z80
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reg reset_n, clk, int_n, sound_clk;
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reg reset_n, clk, int_n, sound_clk;
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initial begin
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initial begin
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//$dumpfile("dump.lxt");
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/* $dumpfile("dump.lxt");
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//$dumpvars(1,map.ym2203_0);
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$dumpvars(1,pwm0);
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$dumpvars(1,pwm1);*/
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// $dumpvars();
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// $dumpvars();
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// $dumpon;
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// $dumpon;
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// $shm_open("1942.shm");
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// $shm_open("1942.shm");
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// $shm_probe( sound1942, "ACTFS" );
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// $shm_probe( sound1942, "ACTFS" );
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reset_n=0;
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reset_n=0;
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#1500 reset_n=1;
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#1500 reset_n=1;
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// change finish time depending on song
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// change finish time depending on song
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//#4e6 $finish;
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//#4e6 $finish;
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#5e9 $finish;
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#6e9 $finish;
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end
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end
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always begin // main clock
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always begin // main clock
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clk=0;
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clk=0;
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forever clk = #167 ~clk;
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forever clk = #167 ~clk;
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//$display("IRQ request @ %t us",$time/1e6);
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//$display("IRQ request @ %t us",$time/1e6);
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#(int_low_time) int_n=1;
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#(int_low_time) int_n=1;
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end
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end
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end
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end
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always #22676 $display("%d", amp0_y+amp1_y ); // 44.1kHz sample
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wire [3:0] ay0_a, ay0_b, ay0_c, ay1_a, ay1_b, ay1_c;
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wire [3:0] ay0_a, ay0_b, ay0_c, ay1_a, ay1_b, ay1_c;
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computer_1942 #(0) game( .clk(clk), .sound_clk(sound_clk),
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computer_1942 #(0) game( .clk(clk), .sound_clk(sound_clk),
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.int_n(int_n), .reset_n(reset_n),
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.int_n(int_n), .reset_n(reset_n),
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.ay0_a(ay0_a), .ay0_b(ay0_b), .ay0_c(ay0_c),
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.ay0_a(ay0_a), .ay0_b(ay0_b), .ay0_c(ay0_c),
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.ay1_a(ay1_a), .ay1_b(ay1_b), .ay1_c(ay1_c) );
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.ay1_a(ay1_a), .ay1_b(ay1_b), .ay1_c(ay1_c) );
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// sound amplifier:
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// sound amplifier:
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wire [15:0] amp0_y, amp1_y;
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/*
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SQM_AMP amp0( .A(ay0_a), .B(ay0_b), .C(ay0_c), .Y( amp0_y ));
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wire [15:0] amp0_y, amp1_y;
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SQM_AMP amp1( .A(ay1_a), .B(ay1_b), .C(ay1_c), .Y( amp1_y ));
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SQM_AMP amp0( .A(ay0_a), .B(ay0_b), .C(ay0_c), .Y( amp0_y ));
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SQM_AMP amp1( .A(ay1_a), .B(ay1_b), .C(ay1_c), .Y( amp1_y ));
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always #22676 $display("%d", amp0_y+amp1_y ); // 44.1kHz sample
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*/
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reg vhf_clk;
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always begin
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vhf_clk=0;
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forever begin
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if( vhf_clk ) begin
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$display("%d, %d, %d, %d, %d, %d",
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pwm0_a, pwm0_b, pwm0_c, pwm1_a, pwm1_b, pwm1_c );
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end
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#10 vhf_clk <= ~vhf_clk; // 50MHz
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end
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end
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SQM_PWM_1 a0pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay0_a), .pwm(pwm0_a) );
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SQM_PWM_1 b0pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay0_b), .pwm(pwm0_b) );
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SQM_PWM_1 c0pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay0_c), .pwm(pwm0_c) );
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SQM_PWM_1 a1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_a), .pwm(pwm1_a) );
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SQM_PWM_1 b1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_b), .pwm(pwm1_b) );
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SQM_PWM_1 c1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_c), .pwm(pwm1_c) );
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endmodule
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endmodule
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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module computer_1942
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module computer_1942
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#(parameter dump_regs=0) // set to 1 to dump sqmusic registers
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#(parameter dump_regs=0) // set to 1 to dump sqmusic registers
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