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shifted <= raw >> exp;
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shifted <= raw >> exp;
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end
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end
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endmodule
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endmodule
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///////////////////////////////////////////////////////////////////
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// sq_opn_eg => Envelope generator
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module sq_opn_eg(
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input clk,
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input reset_n,
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input ce_n, // count enable, active low
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input key_on,
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input key_off,
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input [1:0] ks, // key scale
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input [5:0] ar, // attack rate
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input [5:0] dr, // decay rate
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input [5:0] sr, // sustain rate
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input [3:0] rr, // release rate
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input [3:0] sl, // sustain level
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input [3:0] block,
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input [1:0] note,
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input [6:0] tl, // total level
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output reg [6:0] env, // envelope
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output onwait // EG is on wait state
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);
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reg [2:0] state;
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/*
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reg [6:0] f_ar, // final attack rate
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f_dr, // final decay rate
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f_sr, // final sustain rate
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f_rr; // final release rate
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*/
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parameter st_wait = 3'd0; // wait for key_on
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parameter st_attack = 3'd1;
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parameter st_decay = 3'd2;
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parameter st_sustain= 3'd3;
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parameter st_release= 3'd4;
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assign onwait = state == st_wait;
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reg [7:0] cr; // current rate used for calculations
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reg [7:0] f_sl; // final sustain level: f_sl = tl+sl
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wire [7:0] next_env = { 1'b0, env } + cr;
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wire attack_over = next_env <= tl || next_env>env;
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wire decay_over = next_env >= f_sl;
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wire sustain_over= next_env >= 8'h7F;
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//wire neg = next_env[7];
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always @(posedge clk or negedge reset_n ) begin
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if( !reset_n ) begin
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state <= st_wait;
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env <= 7'h7F;
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end
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else begin
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case( state )
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st_wait:
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if( key_on ) begin
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state <= st_attack;
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cr <= ~ { 2'b0, ar, ar[0] } + 1'b1;
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env <= 7'h7F; // is it ok to reset it?
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f_sl <= { 2'b0, sl, 2'b0 } + {1'b0, tl }; // f_sl = sl + tl
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end
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else begin
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state <=st_wait;
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env <= 7'h7F;
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end
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st_attack:
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if( !ce_n )
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if( attack_over ) begin
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env <= tl;
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cr <= { 2'b0, dr, dr[0] };
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state <= st_decay;
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f_sl <= f_sl[7] ? 8'h7F : f_sl; // clamp the result to 7F
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end
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else begin
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env <= next_env;
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state <= st_attack;
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end
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st_decay:
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if( !ce_n )
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if( decay_over ) begin
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env <= f_sl;
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cr <= { 2'b0, sr, sr[0] };
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state <= st_sustain;
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end
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else begin
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env <= next_env;
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state <= st_decay;
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end
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st_sustain:
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if( key_off ) begin
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env <= next_env;
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cr <= { 1'b0, rr, 3'b0 };
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state <= st_release;
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end
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else
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if( sustain_over ) begin
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if( !ce_n ) begin
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env <= 7'h7F;
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state <= st_wait;
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end
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end
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else if( !ce_n ) begin
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env <= next_env;
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state <= st_sustain;
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end
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st_release:
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if( sustain_over ) begin
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env <= 7'h7F;
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state <= st_wait;
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end
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else if( !ce_n ) begin
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env <= next_env;
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state <= st_release;
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end
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default: begin
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state <=st_wait;
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env <= 7'h7F;
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end
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endcase
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end
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end
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endmodule
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