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`timescale 1ns/1ns
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module bench_fifo_b;
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reg clk, reset;
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localparam width = 16, depth=32, asz=$clog2(depth), usz=$clog2(depth+1);
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initial clk = 0;
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always #10 clk = ~clk;
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reg gen_commit, gen_abort;
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reg chk_commit, chk_abort;
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reg fail;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [width-1:0] chk_data; // From fifo_s of sd_fifo_b.v
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wire chk_drdy; // From chk of sd_seq_check.v
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wire chk_srdy; // From fifo_s of sd_fifo_b.v
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wire [usz-1:0] chk_usage; // From fifo_s of sd_fifo_b.v
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wire [width-1:0] gen_data; // From gen of sd_seq_gen.v
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wire gen_drdy; // From fifo_s of sd_fifo_b.v
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wire gen_srdy; // From gen of sd_seq_gen.v
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wire [usz-1:0] gen_usage; // From fifo_s of sd_fifo_b.v
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// End of automatics
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/* sd_seq_gen AUTO_TEMPLATE
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(
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.p_\(.*\) (gen_\1[]),
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);
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*/
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sd_seq_gen #(width) gen
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(/*AUTOINST*/
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// Outputs
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.p_srdy (gen_srdy), // Templated
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.p_data (gen_data[width-1:0]), // Templated
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// Inputs
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.clk (clk),
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.reset (reset),
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.p_drdy (gen_drdy)); // Templated
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/* sd_seq_check AUTO_TEMPLATE
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(
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.c_\(.*\) (chk_\1[]),
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);
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*/
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sd_seq_check #(width) chk
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(/*AUTOINST*/
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// Outputs
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.c_drdy (chk_drdy), // Templated
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// Inputs
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.clk (clk),
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.reset (reset),
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.c_srdy (chk_srdy), // Templated
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.c_data (chk_data[width-1:0])); // Templated
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/* sd_fifo_b AUTO_TEMPLATE
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(
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.p_\(.*\) (chk_\1[]),
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.c_\(.*\) (gen_\1[]),
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);
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*/
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sd_fifo_b #(width, depth, 1, 1) fifo_b
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(/*AUTOINST*/
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// Outputs
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.c_drdy (gen_drdy), // Templated
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.p_srdy (chk_srdy), // Templated
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.p_data (chk_data[width-1:0]), // Templated
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.p_usage (chk_usage[usz-1:0]), // Templated
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.c_usage (gen_usage[usz-1:0]), // Templated
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// Inputs
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.clk (clk),
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.reset (reset),
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.c_srdy (gen_srdy), // Templated
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.c_commit (gen_commit), // Templated
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.c_abort (gen_abort), // Templated
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.c_data (gen_data[width-1:0]), // Templated
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.p_drdy (chk_drdy), // Templated
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.p_commit (chk_commit), // Templated
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.p_abort (chk_abort)); // Templated
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initial
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begin
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`ifdef VCS
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$vcdpluson;
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`else
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$dumpfile("fifo_b.lxt");
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$dumpvars;
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`endif
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reset = 1;
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gen.rep_count = 0;
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gen_commit = 0;
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gen_abort = 0;
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chk_commit = 1;
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chk_abort = 0;
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fail = 0;
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#100;
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reset = 0;
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repeat (5) @(posedge clk);
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do_reset();
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test1();
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do_reset();
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test2();
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do_reset();
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test3();
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if (fail)
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$display ("!!!!! TEST FAILED !!!!!");
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else
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$display ("----- TEST PASSED -----");
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$finish;
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end // initial begin
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task do_reset;
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begin
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gen.rep_count = 0;
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gen_commit = 0;
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gen_abort = 0;
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chk_commit = 1;
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chk_abort = 0;
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reset = 1;
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repeat (5) @(posedge clk);
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reset = 0;
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repeat (10) @(posedge clk);
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end
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endtask // do_reset
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task end_check;
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begin
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if (chk.err_cnt > 0)
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fail = 1;
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end
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endtask
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// test basic overflow/underflow
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task test1;
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begin
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$display ("Running test 1");
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gen_commit = 1;
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//gen.rep_count = 2000;
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fork
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begin : traffic_gen
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gen.send (depth * 2);
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repeat (5) @(posedge clk);
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gen.srdy_pat = 8'h5A;
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gen.send (depth * 2);
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repeat (5) @(posedge clk);
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chk.drdy_pat = 8'hA5;
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gen.send (depth * 2);
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// check FIFO overflow
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repeat (5) @(posedge clk);
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gen.srdy_pat = 8'hFD;
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gen.send (depth * 4);
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// check FIFO underflow
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repeat (5) @(posedge clk);
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gen.srdy_pat = 8'h11;
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gen.send (depth * 4);
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repeat (20) @(posedge clk);
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disable t1_timeout;
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end // block: traffic_gen
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begin : t1_timeout
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repeat (50 * depth)
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@(posedge clk);
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fail = 1;
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disable traffic_gen;
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$display ("%t: ERROR: test1 timeout", $time);
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end
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join
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#500;
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end_check();
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end
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endtask // test1
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// test of write commit/abort behavior
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task test2;
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begin
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$display ("Running test 2");
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// first fill up entire FIFO
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//chk.drdy_pat = 0;
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gen_commit = 0;
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gen.send (depth-1);
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#50;
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wait (gen_drdy == 0);
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@(posedge clk);
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gen_abort <= #1 1;
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@(posedge clk);
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gen_abort <= #1 0;
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#5;
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if (gen_drdy !== 1)
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begin
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$display ("%t: ERROR -- drdy should be asserted on empty FIFO", $time);
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fail = 1;
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#100 $finish;
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end
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gen.send (depth-2);
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@(posedge clk);
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gen_commit <= 1;
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gen.send (1);
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gen_commit <= 0;
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repeat (depth+10)
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@(posedge clk);
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if (chk.last_seq != (depth*2-2))
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begin
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$display ("%t: ERROR -- last sequence number incorrect (%x)", $time, chk.last_seq);
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fail = 1;
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$finish;
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end
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#5000;
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end_check();
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end
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endtask // test2
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// test read/commit behavior
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task test3;
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begin
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$display ("Running test 3");
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// fill up FIFO
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gen_commit <= 1;
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chk_commit <= 0;
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chk_abort <= 0;
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@(negedge clk);
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chk.drdy_pat = 0;
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chk.c_drdy = 0;
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chk.nxt_c_drdy = 0;
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repeat (10) @(posedge clk);
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gen.send (depth-1);
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// read out contents of FIFO
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chk.drdy_pat = 8'h5A;
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repeat (depth*2+2)
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@(posedge clk);
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chk.drdy_pat = 0;
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// FIFO should be full at this point to write side, and empty to
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// read side
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if (gen_drdy || chk_srdy)
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begin
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$display ("ERROR -- c_drdy or p_srdy asserted");
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fail = 1;
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#100 $finish;
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end
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// reset the read pointer and the expected value
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chk.last_seq = 0;
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chk_abort <= #1 1;
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@(posedge clk);
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chk_abort <= #1 0;
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// read out contents of FIFO again
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chk.drdy_pat = 8'hFF;
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@(posedge clk);
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repeat (depth-3) @(posedge clk);
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chk_commit <= #1 1;
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repeat (4) @(posedge clk);
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chk_commit <= #1 0;
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// All data has been committed, so drdy should be asserted
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if (gen_drdy !== 1)
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begin
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$display ("%t: ERROR -- c_drdy not asserted", $time);
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fail = 1;
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#100 $finish;
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end
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#500;
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end_check();
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end
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endtask
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endmodule // bench_fifo_s
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// Local Variables:
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// verilog-library-directories:("." "../common" "../../../rtl/verilog/buffers")
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// End:
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No newline at end of file
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