URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [bridge.vh] - Diff between revs 5 and 8

Rev 5	Rev 8
Line 31...	Line 31...
`define PCC_SOP 2'b01 // Start of packet	`define PCC_SOP 2'b01 // Start of packet
`define PCC_DATA 2'b00 // data word	`define PCC_DATA 2'b00 // data word
`define PCC_EOP 2'b10 // End of packet	`define PCC_EOP 2'b10 // End of packet
`define PCC_BADEOP 2'b11 // End of packet w/ error	`define PCC_BADEOP 2'b11 // End of packet w/ error

	`// Packet FIFO Word`
	`// uses same field definitions as Packet Ring Word, but no PVEC bit`
	`define PFW_SZ 69

	`// Port FIFO sizes`
	`define RX_FIFO_DEPTH 64
	`define TX_FIFO_DEPTH 256

	`define RX_USG_SZ $clog2(`RX_FIFO_DEPTH)+1
	`define TX_USG_SZ $clog2(`TX_FIFO_DEPTH)+1

`// Packet Ring Word`	`// Packet Ring Word`

`define PRW_SZ 70	`define PRW_SZ 70
`define PRW_DATA 63:0 // 64 bits of packet data	`define PRW_DATA 63:0 // 64 bits of packet data
`define PRW_PCC 65:64 // packet control code	`define PRW_PCC 65:64 // packet control code
`define PRW_VALID 68:66 // # of valid bytes modulo 8	`define PRW_VALID 68:66 // # of valid bytes modulo 8
`define PRW_PVEC 69 // indicates this is port vector word	`define PRW_PVEC 69 // indicates this is port vector word

`No newline at end of file`	`No newline at end of file`
	`// GMII definitions`
	`define GMII_PRE 8'h55
	`define GMII_SFD 8'hD5

`No newline at end of file`	`No newline at end of file`