| Line 1... |
Line 1... |
module distributor
|
module distributor
|
#(parameter width=8)
|
|
(input clk,
|
(input clk,
|
input reset,
|
input reset,
|
|
|
input ptx_srdy,
|
input ptx_srdy,
|
output ptx_drdy,
|
output ptx_drdy,
|
| Line 11... |
Line 10... |
input p_drdy,
|
input p_drdy,
|
output [1:0] p_code,
|
output [1:0] p_code,
|
output [7:0] p_data
|
output [7:0] p_data
|
);
|
);
|
|
|
wire [width-1:0] ic_data; // From body of template_body_1i1o.v
|
reg [7:0] ic_data;
|
wire ic_drdy; // From sdout of sd_output.v
|
reg [1:0] ic_code;
|
wire ic_srdy; // From body of template_body_1i1o.v
|
wire ic_drdy;
|
wire [width-1:0] ip_data; // From sdin of sd_input.v
|
reg ic_srdy;
|
wire ip_drdy; // From body of template_body_1i1o.v
|
wire [`PFW_SZ-1:0] ip_data;
|
wire ip_srdy; // From sdin of sd_input.v
|
reg ip_drdy;
|
// End of automatics
|
wire ip_srdy;
|
|
reg [7:0] remain, nxt_remain;
|
|
|
sd_input #(width) sdin
|
sd_input #(`PFW_SZ) sdin
|
(/*AUTOINST*/
|
(
|
// Outputs
|
// Outputs
|
.c_drdy (c_drdy),
|
.c_drdy (ptx_drdy),
|
.ip_srdy (ip_srdy),
|
.ip_srdy (ip_srdy),
|
.ip_data (ip_data[width-1:0]),
|
.ip_data (ip_data),
|
// Inputs
|
// Inputs
|
.clk (clk),
|
.clk (clk),
|
.reset (reset),
|
.reset (reset),
|
.c_srdy (c_srdy),
|
.c_srdy (ptx_srdy),
|
.c_data (c_data[width-1:0]),
|
.c_data (ptx_data),
|
.ip_drdy (ip_drdy));
|
.ip_drdy (ip_drdy));
|
|
|
template_body_1i1o #(width) body
|
always @*
|
(/*AUTOINST*/
|
begin
|
// Outputs
|
nxt_remain = remain;
|
.ic_data (ic_data[width-1:0]),
|
ic_srdy = 0;
|
.ic_srdy (ic_srdy),
|
ip_drdy = 0;
|
.ip_drdy (ip_drdy),
|
|
// Inputs
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.ic_drdy (ic_drdy),
|
|
.ip_data (ip_data[width-1:0]),
|
|
.ip_srdy (ip_srdy));
|
|
|
|
sd_output #(width) sdout
|
case (remain)
|
(/*AUTOINST*/
|
0 : ic_data = ip_data[63:56];
|
// Outputs
|
7 : ic_data = ip_data[55:48];
|
.ic_drdy (ic_drdy),
|
6 : ic_data = ip_data[47:40];
|
.p_srdy (p_srdy),
|
5 : ic_data = ip_data[39:32];
|
.p_data (p_data[width-1:0]),
|
4 : ic_data = ip_data[31:24];
|
// Inputs
|
3 : ic_data = ip_data[23:16];
|
.clk (clk),
|
2 : ic_data = ip_data[15: 8];
|
.reset (reset),
|
1 : ic_data = ip_data[ 7: 0];
|
.ic_srdy (ic_srdy),
|
default : ic_data = ip_data[63:56];
|
.ic_data (ic_data[width-1:0]),
|
endcase
|
.p_drdy (p_drdy));
|
|
|
|
endmodule // template_1i1o
|
if (ip_srdy & ic_drdy)
|
|
begin
|
|
if (remain == 0)
|
|
begin
|
|
ic_srdy = 1;
|
|
if (ip_data[`PRW_VALID] == 0)
|
|
nxt_remain = 7;
|
|
else
|
|
nxt_remain = ip_data[`PRW_VALID]-1;
|
|
|
module template_body_1i1o
|
if (nxt_remain == 0)
|
#(parameter width=8)
|
ip_drdy = 1;
|
(input clk,
|
|
input reset,
|
|
output reg [width-1:0] ic_data,
|
|
output reg ic_srdy,
|
|
output reg ip_drdy,
|
|
input ic_drdy,
|
|
input [width-1:0] ip_data,
|
|
input ip_srdy
|
|
);
|
|
|
|
always @*
|
if (ip_data[`PRW_PCC] == `PCC_SOP)
|
begin
|
ic_code = `PCC_SOP;
|
ic_data = ip_data;
|
else
|
if (ip_srdy & ip_drdy)
|
ic_code = `PCC_DATA;
|
|
end // if (remain == 0)
|
|
else
|
begin
|
begin
|
ic_srdy = 1;
|
ic_srdy = 1;
|
|
nxt_remain = remain - 1;
|
|
if (nxt_remain == 0)
|
|
begin
|
ip_drdy = 1;
|
ip_drdy = 1;
|
|
if ((ip_data[`PRW_PCC] == `PCC_EOP) |
|
|
(ip_data[`PRW_PCC] == `PCC_BADEOP))
|
|
ic_code = ip_data[`PRW_PCC];
|
|
else
|
|
ic_code = `PCC_DATA;
|
end
|
end
|
else
|
else
|
begin
|
ic_code = `PCC_DATA;
|
ic_srdy = 0;
|
end // else: !if(remain == 0)
|
ip_drdy = 0;
|
|
end
|
end
|
|
end // always @ *
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset)
|
|
remain <= #1 0;
|
|
else
|
|
remain <= #1 nxt_remain;
|
end
|
end
|
|
|
endmodule // template_body_1i1o
|
sd_output #(8+2) sdout
|
|
(
|
|
// Outputs
|
|
.ic_drdy (ic_drdy),
|
|
.p_srdy (p_srdy),
|
|
.p_data ({p_code,p_data}),
|
|
// Inputs
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.ic_srdy (ic_srdy),
|
|
.ic_data ({ic_code,ic_data}),
|
|
.p_drdy (p_drdy));
|
|
|
|
endmodule // template_1i1o
|
|
|
// Local Variables:
|
// Local Variables:
|
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
|
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
|
// End:
|
// End:
|
|
|
No newline at end of file
|
No newline at end of file
|
