| Line 28... |
Line 28... |
wire [`FIB_ENTRY_SZ-1:0] ft_rdata;
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wire [`FIB_ENTRY_SZ-1:0] ft_rdata;
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wire [`PAR_DATA_SZ-1:0] lpp_data;
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wire [`PAR_DATA_SZ-1:0] lpp_data;
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [`FIB_ASZ-1:0] ft_addr; // From fsm0 of fib_lookup_fsm.v
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wire [`FIB_ASZ-1:0] ft_addr; // From fsm0 of fib_lookup_fsm.v
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wire ft_rd_n; // From fsm0 of fib_lookup_fsm.v
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wire ft_rd_en; // From fsm0 of fib_lookup_fsm.v
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wire [`FIB_ENTRY_SZ-1:0] ft_wdata; // From fsm0 of fib_lookup_fsm.v
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wire [`FIB_ENTRY_SZ-1:0] ft_wdata; // From fsm0 of fib_lookup_fsm.v
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wire ft_wr_n; // From fsm0 of fib_lookup_fsm.v
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wire ft_wr_en; // From fsm0 of fib_lookup_fsm.v
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wire [`NUM_PORTS-1:0] lout_data; // From fsm0 of fib_lookup_fsm.v
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wire [`NUM_PORTS-1:0] lout_data; // From fsm0 of fib_lookup_fsm.v
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wire lout_drdy; // From fib_res_out of sd_mirror.v
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wire lout_drdy; // From fib_res_out of sd_mirror.v
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wire [`NUM_PORTS-1:0] lout_dst_vld; // From fsm0 of fib_lookup_fsm.v
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wire lout_srdy; // From fsm0 of fib_lookup_fsm.v
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wire lout_srdy; // From fsm0 of fib_lookup_fsm.v
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wire lpp_drdy; // From fsm0 of fib_lookup_fsm.v
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wire lpp_drdy; // From fsm0 of fib_lookup_fsm.v
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wire lpp_srdy; // From port_parse_in of sd_input.v
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wire lpp_srdy; // From port_parse_in of sd_input.v
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// End of automatics
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// End of automatics
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| Line 70... |
Line 71... |
behave1p_mem #(`FIB_ENTRIES, `FIB_ENTRY_SZ) fib_mem
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behave1p_mem #(`FIB_ENTRIES, `FIB_ENTRY_SZ) fib_mem
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.d_out (ft_rdata), // Templated
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.d_out (ft_rdata), // Templated
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// Inputs
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// Inputs
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.wr_n (ft_wr_n), // Templated
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.wr_en (ft_wr_en), // Templated
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.rd_n (ft_rd_n), // Templated
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.rd_en (ft_rd_en), // Templated
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.clk (clk), // Templated
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.clk (clk), // Templated
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.d_in (ft_wdata), // Templated
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.d_in (ft_wdata), // Templated
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.addr (ft_addr)); // Templated
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.addr (ft_addr)); // Templated
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fib_lookup_fsm fsm0
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fib_lookup_fsm fsm0
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.lpp_drdy (lpp_drdy),
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.lpp_drdy (lpp_drdy),
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.ft_wdata (ft_wdata[`FIB_ENTRY_SZ-1:0]),
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.ft_wdata (ft_wdata[`FIB_ENTRY_SZ-1:0]),
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.ft_rd_n (ft_rd_n),
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.ft_rd_en (ft_rd_en),
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.ft_wr_n (ft_wr_n),
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.ft_wr_en (ft_wr_en),
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.ft_addr (ft_addr[`FIB_ASZ-1:0]),
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.ft_addr (ft_addr[`FIB_ASZ-1:0]),
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.lout_data (lout_data[`NUM_PORTS-1:0]),
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.lout_data (lout_data[`NUM_PORTS-1:0]),
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.lout_srdy (lout_srdy),
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.lout_srdy (lout_srdy),
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.lout_dst_vld (lout_dst_vld[`NUM_PORTS-1:0]),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.lpp_data (lpp_data[`PAR_DATA_SZ-1:0]),
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.lpp_data (lpp_data[`PAR_DATA_SZ-1:0]),
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.lpp_srdy (lpp_srdy),
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.lpp_srdy (lpp_srdy),
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| Line 111... |
Line 113... |
// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.c_srdy (lout_srdy), // Templated
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.c_srdy (lout_srdy), // Templated
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.c_data (lout_data), // Templated
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.c_data (lout_data), // Templated
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.c_dst_vld (lout_dst_vld), // Templated
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.p_drdy (flo_drdy)); // Templated
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.p_drdy (flo_drdy)); // Templated
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endmodule // fib_lookup
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endmodule // fib_lookup
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// Local Variables:
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// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
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// End:
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No newline at end of file
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No newline at end of file
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