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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [fib_lookup.v] - Diff between revs 4 and 5

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Line 28... Line 28...
  wire [`FIB_ENTRY_SZ-1:0] ft_rdata;
  wire [`FIB_ENTRY_SZ-1:0] ft_rdata;
  wire [`PAR_DATA_SZ-1:0] lpp_data;
  wire [`PAR_DATA_SZ-1:0] lpp_data;
  /*AUTOWIRE*/
  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire [`FIB_ASZ-1:0]   ft_addr;                // From fsm0 of fib_lookup_fsm.v
  wire [`FIB_ASZ-1:0]   ft_addr;                // From fsm0 of fib_lookup_fsm.v
  wire                  ft_rd_n;                // From fsm0 of fib_lookup_fsm.v
  wire                  ft_rd_en;               // From fsm0 of fib_lookup_fsm.v
  wire [`FIB_ENTRY_SZ-1:0] ft_wdata;            // From fsm0 of fib_lookup_fsm.v
  wire [`FIB_ENTRY_SZ-1:0] ft_wdata;            // From fsm0 of fib_lookup_fsm.v
  wire                  ft_wr_n;                // From fsm0 of fib_lookup_fsm.v
  wire                  ft_wr_en;               // From fsm0 of fib_lookup_fsm.v
  wire [`NUM_PORTS-1:0] lout_data;              // From fsm0 of fib_lookup_fsm.v
  wire [`NUM_PORTS-1:0] lout_data;              // From fsm0 of fib_lookup_fsm.v
  wire                  lout_drdy;              // From fib_res_out of sd_mirror.v
  wire                  lout_drdy;              // From fib_res_out of sd_mirror.v
 
  wire [`NUM_PORTS-1:0] lout_dst_vld;           // From fsm0 of fib_lookup_fsm.v
  wire                  lout_srdy;              // From fsm0 of fib_lookup_fsm.v
  wire                  lout_srdy;              // From fsm0 of fib_lookup_fsm.v
  wire                  lpp_drdy;               // From fsm0 of fib_lookup_fsm.v
  wire                  lpp_drdy;               // From fsm0 of fib_lookup_fsm.v
  wire                  lpp_srdy;               // From port_parse_in of sd_input.v
  wire                  lpp_srdy;               // From port_parse_in of sd_input.v
  // End of automatics
  // End of automatics
 
 
Line 70... Line 71...
  behave1p_mem #(`FIB_ENTRIES, `FIB_ENTRY_SZ) fib_mem
  behave1p_mem #(`FIB_ENTRIES, `FIB_ENTRY_SZ) fib_mem
    (/*AUTOINST*/
    (/*AUTOINST*/
     // Outputs
     // Outputs
     .d_out                             (ft_rdata),              // Templated
     .d_out                             (ft_rdata),              // Templated
     // Inputs
     // Inputs
     .wr_n                              (ft_wr_n),               // Templated
     .wr_en                             (ft_wr_en),              // Templated
     .rd_n                              (ft_rd_n),               // Templated
     .rd_en                             (ft_rd_en),              // Templated
     .clk                               (clk),                   // Templated
     .clk                               (clk),                   // Templated
     .d_in                              (ft_wdata),              // Templated
     .d_in                              (ft_wdata),              // Templated
     .addr                              (ft_addr));               // Templated
     .addr                              (ft_addr));               // Templated
 
 
  fib_lookup_fsm fsm0
  fib_lookup_fsm fsm0
    (/*AUTOINST*/
    (/*AUTOINST*/
     // Outputs
     // Outputs
     .lpp_drdy                          (lpp_drdy),
     .lpp_drdy                          (lpp_drdy),
     .ft_wdata                          (ft_wdata[`FIB_ENTRY_SZ-1:0]),
     .ft_wdata                          (ft_wdata[`FIB_ENTRY_SZ-1:0]),
     .ft_rd_n                           (ft_rd_n),
     .ft_rd_en                          (ft_rd_en),
     .ft_wr_n                           (ft_wr_n),
     .ft_wr_en                          (ft_wr_en),
     .ft_addr                           (ft_addr[`FIB_ASZ-1:0]),
     .ft_addr                           (ft_addr[`FIB_ASZ-1:0]),
     .lout_data                         (lout_data[`NUM_PORTS-1:0]),
     .lout_data                         (lout_data[`NUM_PORTS-1:0]),
     .lout_srdy                         (lout_srdy),
     .lout_srdy                         (lout_srdy),
 
     .lout_dst_vld                      (lout_dst_vld[`NUM_PORTS-1:0]),
     // Inputs
     // Inputs
     .clk                               (clk),
     .clk                               (clk),
     .reset                             (reset),
     .reset                             (reset),
     .lpp_data                          (lpp_data[`PAR_DATA_SZ-1:0]),
     .lpp_data                          (lpp_data[`PAR_DATA_SZ-1:0]),
     .lpp_srdy                          (lpp_srdy),
     .lpp_srdy                          (lpp_srdy),
Line 111... Line 113...
     // Inputs
     // Inputs
     .clk                               (clk),
     .clk                               (clk),
     .reset                             (reset),
     .reset                             (reset),
     .c_srdy                            (lout_srdy),             // Templated
     .c_srdy                            (lout_srdy),             // Templated
     .c_data                            (lout_data),             // Templated
     .c_data                            (lout_data),             // Templated
 
     .c_dst_vld                         (lout_dst_vld),          // Templated
     .p_drdy                            (flo_drdy));              // Templated
     .p_drdy                            (flo_drdy));              // Templated
 
 
endmodule // fib_lookup
endmodule // fib_lookup
 
// Local Variables:
 
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
 
// End:  
 
 
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