OpenCores

Rev 8	Rev 11
Line 25...	Line 25...
`);`	`);`

`reg [4:0] state, nxt_state;`	`reg [4:0] state, nxt_state;`

wire [`NUM_PORTS-1:0] port_mask;	wire [`NUM_PORTS-1:0] port_mask;
reg [`NUM_PORTS-1:0] pe_vec, nxt_pe_vec;	//reg [`NUM_PORTS-1:0] pe_vec, nxt_pe_vec;
	wire [`NUM_PORTS-1:0] nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;

`assign port_mask = 1 << portnum;`	`assign port_mask = 1 << portnum;`

`localparam s_idle = 0,`	`localparam s_idle = 0,`
`s_rfwd = 1,`	`s_rfwd = 1,`
Line 75...	Line 76...
`else if (lri_srdy)`	`else if (lri_srdy)`
`begin`	`begin`
if (lri_data[`PRW_DATA] & port_mask)	if (lri_data[`PRW_DATA] & port_mask)
`begin`	`begin`
`// packet is for our port`	`// packet is for our port`
nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;	//nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;

`// if enable vector is not empty, send the`	`// if enable vector is not empty, send the`
`// vector to the next port`	`// vector to the next port`
`if ((nxt_pe_vec != 0) & lro_drdy)`	`if ((nxt_pe_vec != 0) & lro_drdy)`
`begin`	`begin`
Line 87...	Line 88...
lro_data[`PRW_PVEC] = 1;	lro_data[`PRW_PVEC] = 1;
`lro_srdy = 1;`	`lro_srdy = 1;`
`lri_drdy = 1;`	`lri_drdy = 1;`
`nxt_state = ns_rcopy;`	`nxt_state = ns_rcopy;`
`end`	`end`
`else`	`else if (nxt_pe_vec == 0)`
`begin`	`begin`
`lri_drdy = 1;`	`lri_drdy = 1;`
`nxt_state = ns_rsink;`	`nxt_state = ns_rsink;`
`end // else: !if((nxt_pe_vec != 0) & lro_drdy)`	`end // else: !if((nxt_pe_vec != 0) & lro_drdy)`
end // if (lri_data[`PRW_DATA] & port_mask)	end // if (lri_data[`PRW_DATA] & port_mask)
Line 155...	Line 156...
`end`	`end`
`end`	`end`

`// data on ring is for our port and we are the last port`	`// data on ring is for our port and we are the last port`
`// copy ring data to our TX buffer but do not copy to ring`	`// copy ring data to our TX buffer but do not copy to ring`
`state[s_rcopy] :`	`state[s_rsink] :`
`begin`	`begin`
lptx_data = lri_data[`PFW_SZ-1:0];	lptx_data = lri_data[`PFW_SZ-1:0];
`if (lri_srdy & lptx_drdy)`	`if (lri_srdy & lptx_drdy)`
`begin`	`begin`
`lri_drdy = 1;`	`lri_drdy = 1;`

Line 25...

);

);

  reg [4:0]            state, nxt_state;

  reg [4:0]            state, nxt_state;

  wire [`NUM_PORTS-1:0] port_mask;

  wire [`NUM_PORTS-1:0] port_mask;

  reg [`NUM_PORTS-1:0]  pe_vec, nxt_pe_vec;

  //reg [`NUM_PORTS-1:0]  pe_vec, nxt_pe_vec;

  wire [`NUM_PORTS-1:0] nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;

  assign port_mask = 1 << portnum;

  assign port_mask = 1 << portnum;

  localparam s_idle = 0,

  localparam s_idle = 0,

             s_rfwd = 1,

             s_rfwd = 1,

Line 75...

Line 76...

            else if (lri_srdy)

            else if (lri_srdy)

              begin

              begin

                if (lri_data[`PRW_DATA] & port_mask)

                if (lri_data[`PRW_DATA] & port_mask)

                  begin

                  begin

                    // packet is for our port

                    // packet is for our port

                    nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;

                    //nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;

                    // if enable vector is not empty, send the

                    // if enable vector is not empty, send the

                    // vector to the next port

                    // vector to the next port

                    if ((nxt_pe_vec != 0) & lro_drdy)

                    if ((nxt_pe_vec != 0) & lro_drdy)

                      begin

                      begin

Line 87...

Line 88...

                        lro_data[`PRW_PVEC] = 1;

                        lro_data[`PRW_PVEC] = 1;

                        lro_srdy = 1;

                        lro_srdy = 1;

                        lri_drdy = 1;

                        lri_drdy = 1;

                        nxt_state = ns_rcopy;

                        nxt_state = ns_rcopy;

end

end

                    else

                    else if (nxt_pe_vec == 0)

                      begin

                      begin

                        lri_drdy = 1;

                        lri_drdy = 1;

                        nxt_state = ns_rsink;

                        nxt_state = ns_rsink;

                      end // else: !if((nxt_pe_vec != 0) & lro_drdy)

                      end // else: !if((nxt_pe_vec != 0) & lro_drdy)

                  end // if (lri_data[`PRW_DATA] & port_mask)

                  end // if (lri_data[`PRW_DATA] & port_mask)

Line 155...

Line 156...

end

end

end

end

        // data on ring is for our port and we are the last port

        // data on ring is for our port and we are the last port

        // copy ring data to our TX buffer but do not copy to ring

        // copy ring data to our TX buffer but do not copy to ring

        state[s_rcopy] :

        state[s_rsink] :

          begin

          begin

            lptx_data = lri_data[`PFW_SZ-1:0];

            lptx_data = lri_data[`PFW_SZ-1:0];

            if (lri_srdy & lptx_drdy)

            if (lri_srdy & lptx_drdy)

              begin

              begin

                lri_drdy = 1;

                lri_drdy = 1;

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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_ring_tap_fsm.v] - Diff between revs 8 and 11