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module port_ring_tap_fsm
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module port_ring_tap_fsm
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#(parameter rdp_sz = 64,
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#(parameter rdp_sz = 64,
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parameter pdp_sz = 64,
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parameter portnum = 0)
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parameter portnum = 0)
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(
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(
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input clk,
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input clk,
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input reset,
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input reset,
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output reg lfli_drdy,
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output reg lfli_drdy,
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output reg lprx_drdy,
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output reg lprx_drdy,
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output reg[rdp_sz-1:0] lptx_data,
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output reg[pdp_sz-1:0] lptx_data,
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output reg lptx_srdy,
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output reg lptx_srdy,
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output reg lri_drdy,
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output reg lri_drdy,
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output reg[rdp_sz-1:0] lro_data,
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output reg[rdp_sz-1:0] lro_data,
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output reg lro_srdy,
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output reg lro_srdy,
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input [rdp_sz-1:0] lfli_data,
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input [`NUM_PORTS-1:0] lfli_data,
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input lfli_srdy,
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input lfli_srdy,
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input [rdp_sz-1:0] lprx_data,
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input [pdp_sz-1:0] lprx_data,
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input lprx_srdy,
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input lprx_srdy,
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input lptx_drdy,
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input lptx_drdy,
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input [rdp_sz-1:0] lri_data,
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input [rdp_sz-1:0] lri_data,
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input lri_srdy,
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input lri_srdy,
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input lro_drdy
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input lro_drdy
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// End of automatics
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);
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);
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reg [6:0] state, nxt_state;
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reg [4:0] state, nxt_state;
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wire [`NUM_PORTS-1:0] port_mask;
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wire [`NUM_PORTS-1:0] port_mask;
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reg [`NUM_PORTS-1:0] pe_vec, nxt_pe_vec;
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reg [`NUM_PORTS-1:0] pe_vec, nxt_pe_vec;
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assign port_mask = 1 << portnum;
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assign port_mask = 1 << portnum;
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parameter s_idle = 0,
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localparam s_idle = 0,
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s_rcmd = 1,
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s_rfwd = 1,
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s_rfwd = 2,
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s_rcopy = 2,
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s_rcopy = 3,
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s_rsink = 3,
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s_rsink = 4,
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s_tdata = 4;
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s_tcmd = 5,
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localparam ns_idle = 1,
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s_tdata = 6;
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ns_rfwd = 2,
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ns_rcopy = 4,
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ns_rsink = 8,
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ns_tdata = 16;
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always @*
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always @*
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begin
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begin
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lro_data = lri_data;
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lro_data = lri_data;
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lptx_data = lri_data;
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lfli_drdy = 0;
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lprx_drdy = 0;
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lptx_srdy = 0;
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lri_drdy = 0;
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lro_srdy = 0;
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case (1'b1)
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case (1'b1)
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state[s_idle] :
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state[s_idle] :
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begin
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begin
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if (lfli_srdy)
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if (lfli_srdy)
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begin
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begin
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if (lfli_data != 0)
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begin
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lro_data = 0;
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lro_data[`PRW_PVEC] = 1;
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lro_data[`PRW_DATA] = lfli_data;
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if (lro_drdy)
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begin
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lfli_drdy = 1;
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lro_srdy = 1;
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nxt_state = ns_tdata;
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end
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end
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else
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lfli_drdy = 1;
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end
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end
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else if (lri_srdy)
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else if (lri_srdy)
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begin
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begin
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if (lri_data[`PRW_DATA] & port_mask)
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if (lri_data[`PRW_DATA] & port_mask)
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begin
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begin
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end
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end
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end // else: !if(lri_data[`PRW_DATA] & port_mask)
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end // else: !if(lri_data[`PRW_DATA] & port_mask)
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end // if (lri_srdy)
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end // if (lri_srdy)
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end // case: state[s_idle]
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end // case: state[s_idle]
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// transmit data from port on to the ring
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state[s_tdata] :
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begin
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lro_data = lprx_data;
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lro_data[`PRW_PVEC] = 0;
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if (lro_drdy & lprx_srdy)
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begin
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lprx_drdy = 1;
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lro_srdy = 1;
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if ((lprx_data[`PRW_PCC] == `PCC_EOP) |
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(lprx_data[`PRW_PCC] == `PCC_BADEOP))
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nxt_state = ns_idle;
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end
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end // case: state[s_tdata]
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// data on ring is for our port as well as further ports
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// copy ring data to our TX buffer as well as on the ring
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state[s_rcopy] :
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begin
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lro_data = lri_data;
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lptx_data = lri_data[`PFW_SZ-1:0];
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if (lri_srdy & lro_drdy & lptx_drdy)
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begin
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lri_drdy = 1;
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lro_srdy = 1;
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lptx_srdy = 1;
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if ((lri_data[`PRW_PCC] == `PCC_EOP) |
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(lri_data[`PRW_PCC] == `PCC_BADEOP))
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nxt_state = ns_idle;
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end
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end
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// data on ring is not for our port, copy from ring in to ring out
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state[s_rfwd] :
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begin
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lro_data = lri_data;
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if (lri_srdy & lro_drdy)
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begin
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lri_drdy = 1;
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lro_srdy = 1;
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if ((lri_data[`PRW_PCC] == `PCC_EOP) |
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(lri_data[`PRW_PCC] == `PCC_BADEOP))
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nxt_state = ns_idle;
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end
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end
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// data on ring is for our port and we are the last port
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// copy ring data to our TX buffer but do not copy to ring
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state[s_rcopy] :
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begin
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lptx_data = lri_data[`PFW_SZ-1:0];
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if (lri_srdy & lptx_drdy)
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begin
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lri_drdy = 1;
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lptx_srdy = 1;
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if ((lri_data[`PRW_PCC] == `PCC_EOP) |
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(lri_data[`PRW_PCC] == `PCC_BADEOP))
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nxt_state = ns_idle;
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end
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end
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default : nxt_state = ns_idle;
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default : nxt_state = ns_idle;
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endcase // case (1'b1)
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endcase // case (1'b1)
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end // always @ *
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end // always @ *
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always @(posedge clk)
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begin
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if (reset)
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begin
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state <= #1 1;
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/*AUTORESET*/
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end
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else
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begin
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state <= #1 nxt_state;
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end
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end // always @ (posedge clk)
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endmodule // port_ring_tap_fsm
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endmodule // port_ring_tap_fsm
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