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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_b.v] - Diff between revs 16 and 19

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Rev 16 Rev 19
Line 23... Line 23...
module sd_fifo_b
module sd_fifo_b
  #(parameter width=8,
  #(parameter width=8,
    parameter depth=256,
    parameter depth=256,
    parameter rd_commit=0,
    parameter rd_commit=0,
    parameter wr_commit=0,
    parameter wr_commit=0,
    parameter asz=$clog2(depth)
    parameter asz=$clog2(depth),
 
    parameter usz=$clog2(depth+1)
    )
    )
    (
    (
     input       clk,
     input       clk,
     input       reset,
     input       reset,
 
 
Line 41... Line 42...
     input       p_drdy,
     input       p_drdy,
     input       p_commit,
     input       p_commit,
     input       p_abort,
     input       p_abort,
     output [width-1:0] p_data,
     output [width-1:0] p_data,
 
 
     output [asz:0] p_usage,
     output [usz-1:0] p_usage,
     output [asz:0] c_usage
     output [usz-1:0] c_usage
     );
     );
 
 
  wire [asz-1:0] com_rdptr;              // From tail of sd_fifo_tail_b.v
  wire [asz-1:0] com_rdptr;              // From tail of sd_fifo_tail_b.v
  wire [asz-1:0] com_wrptr;              // From head of sd_fifo_head_b.v
  wire [asz-1:0] com_wrptr;              // From head of sd_fifo_head_b.v
  wire [asz-1:0] cur_rdptr;              // From tail of sd_fifo_tail_b.v
  wire [asz-1:0] cur_rdptr;              // From tail of sd_fifo_tail_b.v
  wire [asz-1:0] cur_wrptr;              // From head of sd_fifo_head_b.v
  wire [asz-1:0] cur_wrptr;              // From head of sd_fifo_head_b.v
  wire [width-1:0]       mem_rd_data;
  wire [width-1:0]       mem_rd_data;
  wire                  mem_re;                 // From tail of sd_fifo_tail_b.v
  wire                  mem_re;                 // From tail of sd_fifo_tail_b.v
  wire                  mem_we;                 // From head of sd_fifo_head_b.v
  wire                  mem_we;                 // From head of sd_fifo_head_b.v
  wire [asz:0]           usage;                  // From tail of sd_fifo_tail_b.v
 
  wire [asz-1:0]         bound_high;
  wire [asz-1:0]         bound_high;
 
 
  assign bound_high = depth-1;
  assign bound_high = depth-1;
 
 
  sd_fifo_head_b #(depth, wr_commit) head
  sd_fifo_head_b #(depth, wr_commit) head

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