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Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_tail_b.v] - Diff between revs 6 and 11

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Rev 6	Rev 11
Line 129...	Line 129...
cur_rdptr <= `SDLIB_DELAY bound_low;	cur_rdptr <= `SDLIB_DELAY bound_low;
`else`	`else`
cur_rdptr <= `SDLIB_DELAY nxt_cur_rdptr;	cur_rdptr <= `SDLIB_DELAY nxt_cur_rdptr;
`end`	`end`

	`reg [asz-1:0] rdaddr_s0, rdaddr_a, rdaddr_b;`
	`reg [asz-1:0] nxt_com_rdptr;`
`generate`	`generate`
`if (commit == 1)`	`if (commit == 1)`
`begin : gen_s0`	`begin : gen_s0`
`reg [asz-1:0] rdaddr_s0, rdaddr_a, rdaddr_b;`
`reg [asz-1:0] nxt_com_rdptr;`

`always @(posedge clk)`	`always @(posedge clk)`
`begin`	`begin`
`if (reset)`	`if (reset)`
com_rdptr <= `SDLIB_DELAY bound_low;	com_rdptr <= `SDLIB_DELAY bound_low;
Line 171...	Line 171...
`end // else: !if(reset)`	`end // else: !if(reset)`
end // always @ (`SDLIB_CLOCKING)	end // always @ (`SDLIB_CLOCKING)

`generate`	`generate`
`if (commit == 1)`	`if (commit == 1)`
`begin`	`begin : gen_s2`
`wire [asz-1:0] ip_rdaddr, p_rdaddr;`	`wire [asz-1:0] ip_rdaddr, p_rdaddr;`

`sd_input #(asz+width) rbuf1`	`sd_input #(asz+width) rbuf1`
`(.clk (clk), .reset (p_abort \| reset),`	`(.clk (clk), .reset (p_abort \| reset),`
`.c_srdy (prev_re),`	`.c_srdy (prev_re),`
Line 199...	Line 199...
`else`	`else`
`nxt_com_rdptr = com_rdptr;`	`nxt_com_rdptr = com_rdptr;`
`end`	`end`
`end // if (commit == 1)`	`end // if (commit == 1)`
`else`	`else`
`begin`	`begin : gen_ns2`
`sd_input #(width) rbuf1`	`sd_input #(width) rbuf1`
`(.clk (clk), .reset (p_abort \| reset),`	`(.clk (clk), .reset (p_abort \| reset),`
`.c_srdy (prev_re),`	`.c_srdy (prev_re),`
`.c_drdy (rbuf1_drdy),`	`.c_drdy (rbuf1_drdy),`
`.c_data (mem_rd_data),`	`.c_data (mem_rd_data),`

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_tail_b.v] - Diff between revs 6 and 11