| Line 62... |
Line 62... |
input p_abort,
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input p_abort,
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input [width-1:0] mem_rd_data,
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input [width-1:0] mem_rd_data,
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output [width-1:0] p_data
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output [width-1:0] p_data
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);
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);
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reg [asz-1:0] cur_rdptr;
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reg [asz-1:0] nxt_cur_rdptr;
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reg [asz-1:0] nxt_cur_rdptr;
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reg [asz-1:0] cur_rdptr_p1;
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reg [asz-1:0] cur_rdptr_p1;
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reg [asz-1:0] com_rdptr;
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reg empty, full;
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reg empty, full;
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reg p_srdy;
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reg nxt_irdy;
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reg nxt_irdy;
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reg [width-1:0] hold_a, hold_b;
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reg [width-1:0] hold_a, hold_b;
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reg valid_a, valid_b;
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reg valid_a, valid_b;
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reg prev_re;
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reg prev_re;
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reg [asz:0] tmp_usage;
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reg [asz:0] tmp_usage;
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reg [asz:0] fifo_size;
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reg [asz:0] fifo_size;
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wire rbuf1_drdy;
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wire ip_srdy, ip_drdy;
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wire [width-1:0] ip_data;
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// Stage 1 -- Read pipeline
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// Stage 1 -- Read pipeline
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// issue a read if:
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// issue a read if:
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// 1) we are enabled
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// 1) we are enabled
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// 2) valid_a is 0, OR
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// 2) valid_a is 0, OR
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| Line 100... |
Line 100... |
if (commit && p_abort)
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if (commit && p_abort)
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begin
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begin
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nxt_cur_rdptr = com_rdptr;
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nxt_cur_rdptr = com_rdptr;
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mem_re = 0;
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mem_re = 0;
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end
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end
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else if (enable & !empty & (!valid_a | (!prev_re & !valid_b) |
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// else if (enable & !empty & (!valid_a | (!prev_re & !valid_b) |
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(valid_a & valid_b & p_drdy)))
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// (valid_a & valid_b & p_drdy)))
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else if (enable & !empty & ip_drdy)
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begin
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begin
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nxt_cur_rdptr = cur_rdptr_p1;
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nxt_cur_rdptr = cur_rdptr_p1;
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mem_re = 1;
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mem_re = 1;
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end
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end
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else
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else
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| Line 157... |
Line 158... |
// Stage 2 -- read buffering
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// Stage 2 -- read buffering
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always @(`SDLIB_CLOCKING)
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always @(`SDLIB_CLOCKING)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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valid_a <= `SDLIB_DELAY 0;
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hold_a <= `SDLIB_DELAY 0;
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prev_re <= `SDLIB_DELAY 0;
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prev_re <= `SDLIB_DELAY 0;
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end
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end
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else
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else
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begin
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begin
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if (commit && p_abort)
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if (commit && p_abort)
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prev_re <= `SDLIB_DELAY 0;
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prev_re <= `SDLIB_DELAY 0;
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else
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else
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prev_re <= `SDLIB_DELAY mem_re;
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prev_re <= `SDLIB_DELAY mem_re;
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end // else: !if(reset)
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if (commit && p_abort)
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end // always @ (`SDLIB_CLOCKING)
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valid_a <= `SDLIB_DELAY 0;
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else if (prev_re)
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begin
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valid_a <= `SDLIB_DELAY 1;
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hold_a <= `SDLIB_DELAY mem_rd_data;
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end
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else if (!valid_b | p_drdy)
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valid_a <= `SDLIB_DELAY 0;
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end
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end // always @ (posedge clk or posedge reset)
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generate
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generate
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if (commit == 1)
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if (commit == 1)
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begin : gen_s2
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always @(posedge clk)
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begin
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if (prev_re)
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rdaddr_a <= `SDLIB_DELAY rdaddr_s0;
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end
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end
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endgenerate
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// Stage 3 -- output irdy/trdy
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always @(`SDLIB_CLOCKING)
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begin
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if (reset)
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begin
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valid_b <= `SDLIB_DELAY 0;
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hold_b <= `SDLIB_DELAY 0;
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end
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else
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begin
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if (commit && p_abort)
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valid_b <= `SDLIB_DELAY 0;
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else if (valid_a & (!valid_b | p_drdy))
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begin
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begin
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valid_b <= `SDLIB_DELAY 1;
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wire [asz-1:0] ip_rdaddr, p_rdaddr;
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hold_b <= `SDLIB_DELAY hold_a;
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end
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else if (valid_b & p_drdy)
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valid_b <= `SDLIB_DELAY 0;
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end
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end // always @ (posedge clk or posedge reset)
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generate
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sd_input #(asz+width) rbuf1
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if (commit == 1)
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(.clk (clk), .reset (p_abort | reset),
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begin : gen_s3
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.c_srdy (prev_re),
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always @(posedge clk)
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.c_drdy (rbuf1_drdy),
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begin
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.c_data ({rdaddr_s0,mem_rd_data}),
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if (valid_a & (!valid_b | p_drdy))
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.ip_srdy (ip_srdy), .ip_drdy (ip_drdy),
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rdaddr_b <= `SDLIB_DELAY rdaddr_a;
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.ip_data ({ip_rdaddr,ip_data}));
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end
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sd_output #(asz+width) rbuf2
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(.clk (clk), .reset (p_abort | reset),
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.ic_srdy (ip_srdy),
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.ic_drdy (ip_drdy),
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.ic_data ({ip_rdaddr,ip_data}),
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.p_srdy (p_srdy), .p_drdy (p_drdy),
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.p_data ({p_rdaddr,p_data}));
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always @*
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always @*
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begin
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begin
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if (p_commit)
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if (p_commit)
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nxt_com_rdptr = rdaddr_b;
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nxt_com_rdptr = p_rdaddr;
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else
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else
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nxt_com_rdptr = com_rdptr;
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nxt_com_rdptr = com_rdptr;
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end
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end
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end
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end // if (commit == 1)
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else
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begin
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sd_input #(width) rbuf1
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(.clk (clk), .reset (p_abort | reset),
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.c_srdy (prev_re),
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.c_drdy (rbuf1_drdy),
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.c_data (mem_rd_data),
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.ip_srdy (ip_srdy), .ip_drdy (ip_drdy),
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.ip_data (ip_data));
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sd_output #(width) rbuf2
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(.clk (clk), .reset (p_abort | reset),
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.ic_srdy (ip_srdy),
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.ic_drdy (ip_drdy),
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.ic_data (ip_data),
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.p_srdy (p_srdy), .p_drdy (p_drdy),
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.p_data (p_data));
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end // else: !if(commit == 1)
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endgenerate
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endgenerate
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assign p_srdy = valid_b;
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assign p_data = hold_b;
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endmodule // it_fifo
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endmodule // it_fifo
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No newline at end of file
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No newline at end of file
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