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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] [sd_ajoin2.v] - Diff between revs 18 and 30

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Rev 18 Rev 30
Line 24... Line 24... 
 
 
 
 
module sd_ajoin2
 
module sd_ajoin2
 
  #(parameter c1_width=8,
 
  #(parameter c1_width=8,
 
    parameter c2_width=8)
 
    parameter c2_width=8)
 
  (
 
  (
 
   input              clk;
 
   input              clk,
 
   input              reset,
 
   input              reset,
 
 
 
 
 
   input              c1_srdy,
 
   input              c1_srdy,
 
   output             c1_drdy,
 
   output             c1_drdy,
 
   input [c1_width-1:0] c1_data,
 
   input [c1_width-1:0] c1_data,

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