| Line 38... |
Line 38... |
---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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-- ----
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---- ----
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-- CVS Revision History ----
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-- CVS Revision History ----
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-- ----
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---- ----
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-- $Log: not supported by cvs2svn $ ----
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-- $Log: not supported by cvs2svn $ ----
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-- ----
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---- ----
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--
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---- ----
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-- quick description
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-- quick description
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--
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--
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-- Based upon the using a shift register as a fifo which has been
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-- Based upon the using a shift register as a fifo which has been
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-- around for years ( decades ), but really came of use to VHDL
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-- around for years ( decades ), but really came of use to VHDL
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-- when the Xilinx FPGA's started having SRL's.
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-- when the Xilinx FPGA's started having SRL's.
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| Line 55... |
Line 55... |
-- In my view, the definitive article on shift register logic fifo's
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-- In my view, the definitive article on shift register logic fifo's
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-- comes from Mr Chapman at Xilinx, in the form of his BBFIFO
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-- comes from Mr Chapman at Xilinx, in the form of his BBFIFO
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-- tecXeclusive article, which as at early 2008, Xilinx have
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-- tecXeclusive article, which as at early 2008, Xilinx have
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-- removed.
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-- removed.
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--
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--
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-- This version is for 'later' devices that have an inherent shift
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-- register of 32 bits.
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--
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--
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-- using Xilinx ISE 10.1 and later, the tools are getting real clever.
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-- In previous version of ISE, SRL inferance was not this clever.
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-- now if one infers a 32 bit srl in a device that has inherantly 16
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-- bit srls, then an srl and a series of registers was created.
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-- In 10,1 and later, if you infer a 32 bit srl for a device with
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-- 16 bit srls in, then you end up with the cascaded srls as expected.
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--
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-- Well done Xilinx..
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--
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.NUMERIC_STD.all;
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use ieee.NUMERIC_STD.all;
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|
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entity srl_fifo_32 is
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entity srl_fifo_32 is
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