| Line 56... |
Line 56... |
- 7 shift and rotation instructions: <<0, <<1, 0>>, 1>>, <>, and lsb>>
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- 7 shift and rotation instructions: <<0, <<1, 0>>, 1>>, <>, and lsb>>
|
- 4 logical instructions: 0=, 0<>, -1=, -1<>
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- 4 logical instructions: 0=, 0<>, -1=, -1<>
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- 6 Forth-like data stack instructions: drop, dup, nip, over, push, swap
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- 6 Forth-like data stack instructions: drop, dup, nip, over, push, swap
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- 3 Forth-like return stack instructions: >r, r>, r@
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- 3 Forth-like return stack instructions: >r, r>, r@
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- 2 I/O: inport, outport
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- 2 I/O: inport, outport
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- 6 memory read and write with optional address post increment and post decrement
|
- 6 memory read and write with optional address post increment or post decrement
|
- 2 jump and conditional jump
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- 2 jump and conditional jump
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- 2 call and conditional call
|
- 2 call and conditional call
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- 1 function return
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- 1 function return
|
- 1 nop
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- 1 nop
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| Line 968... |
Line 968... |
variable name is used to identify the memory instead of
|
variable name is used to identify the memory instead of
|
the name of the memory
|
the name of the memory
|
.fetchram+(var_name) is similar to the .fetch+(mem_name) macro except that
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.fetchram+(var_name) is similar to the .fetch+(mem_name) macro except that
|
the variable name is used to identify the memory instead
|
the variable name is used to identify the memory instead
|
of the name of the memory
|
of the name of the memory
|
.fetchram-(var_name) is similar to the .fetch-(mem_name) macro except that the
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.fetchram-(var_name) is similar to the .fetch-(mem_name) macro except that
|
the variable name is used to identify the memory instead
|
the variable name is used to identify the memory instead
|
of the name of the memory
|
of the name of the memory
|
.fetchvalue(var_name) fetches the single-byte value of var_name
|
.fetchvalue(var_name) fetches the single-byte value of var_name
|
Note: This is equivalent to
|
Note: This is equivalent to
|
"var_name .fetch(mem_name)"
|
"var_name .fetch(mem_name)"
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| Line 1023... |
Line 1023... |
stack:
|
stack:
|
.storevalue(var_name,1-)
|
.storevalue(var_name,1-)
|
.storevector(var_name,N)
|
.storevector(var_name,N)
|
Does the reverse of the .fetchvector macro.
|
Does the reverse of the .fetchvector macro.
|
Note: This is equivalent to the N+2 operation sequence
|
Note: This is equivalent to the N+2 operation sequence
|
"var_name .store+(mem_name) ... .store+(mem_name)
|
"var_name
|
|
.store+(mem_name) ... .store+(mem_name)
|
.store(mem_name) drop"
|
.store(mem_name) drop"
|
where ".store+(mem_name)" is repeated N-1 times.
|
where ".store+(mem_name)" is repeated N-1 times.
|
|
|
The .fetchvector and .storevector macros are intended to work with values stored
|
The .fetchvector and .storevector macros are intended to work with values stored
|
MSB first in memory and with the MSB toward the top of the data stack,
|
MSB first in memory and with the MSB toward the top of the data stack,
|
| Line 1110... |
Line 1111... |
the width of the output signal is accessible using "${size['o_big']}". You can
|
the width of the output signal is accessible using "${size['o_big']}". You can
|
set the wide signal to all zeroes using:
|
set the wide signal to all zeroes using:
|
|
|
${(size['o_big']+7)/8-1} :loop 0 .outport(O_BIG) .jumpc(loop,1-) drop
|
${(size['o_big']+7)/8-1} :loop 0 .outport(O_BIG) .jumpc(loop,1-) drop
|
|
|
|
The sizes of variables, i.e., how many bytes of memory they occupy, are also
|
|
provided.
|
|
|
|
|
MACROS
|
MACROS
|
================================================================================
|
================================================================================
|
|
|
There are 3 types of macros used by the assembler.
|
There are 3 types of macros used by the assembler.
|
| Line 1288... |
Line 1292... |
core and peripheral test benches; Verilator for long simulations of large,
|
core and peripheral test benches; Verilator for long simulations of large,
|
complex systems; and ISIM when Xilinx-specific cores are used. Verilator is
|
complex systems; and ISIM when Xilinx-specific cores are used. Verilator is
|
the fastest simulators I've encountered. Verilator is also used for lint
|
the fastest simulators I've encountered. Verilator is also used for lint
|
checking in the core test benches.
|
checking in the core test benches.
|
|
|
|
The test benches for the core and the peripherals require Icarus Verilog and
|
|
Verilator.
|
|
|
|
|
MEM INITIALIZATION FILE
|
MEM INITIALIZATION FILE
|
================================================================================
|
================================================================================
|
|
|
A memory initialization file is produced during compilation. This file can be
|
A memory initialization file is produced during compilation. This file can be
|
