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SSBCC.9x8 is a free Small Stack-Based Computer Compiler with a 9-bit opcode,
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SSBCC.9x8 is a free Small Stack-Based Computer Compiler with a 9-bit opcode,
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8-bit data core. It creates vendor-independent, high-speed, low fabric
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8-bit data core designed to facilitate FPGA HDL development.
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utilization micro controllers for FPGAs. It has been used in Spartan-3A,
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Spartan-6, Virtex-6, and Artix-7 FPGAs and has been built for Altera, Lattice,
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The primary design criteria are:
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and other Xilinx devices. It is faster and usually smaller than vendor provided
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- high speed (to avoid timing issues)
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processors.
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- low fabric utilization
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- vendor independent
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- development tools available for all operating systems
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It has been used in Spartan-3A, Spartan-6, Virtex-6, and Artix-7 FPGAs and has
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been built for Altera, Lattice, and other Xilinx devices. It is faster and
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usually smaller than vendor provided processors.
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The compiler takes an architecture file that describes the micro controller
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The compiler takes an architecture file that describes the micro controller
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memory spaces, inputs and outputs, and peripherals and which specifies the HDL
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memory spaces, inputs and outputs, and peripherals and which specifies the HDL
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language and source assembly. It generates a single HDL module implementing
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language and source assembly. It generates a single HDL module implementing
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the entire micro controller. No user-written HDL is required to instantiate
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the entire micro controller. No user-written HDL is required to instantiate
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I/Os, program memory, etc.
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I/Os, program memory, etc.
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The features are:
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- high speed, low fabric utilization
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- vendor-independent Verilog output with a VHDL package file
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- simple Forth-like assembly language (41 instructions)
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- single cycle instruction execution
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- automatic generation of I/O ports
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- configurable instruction, data stack, return stack, and memory utilization
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- extensible set of peripherals (I2C busses, UARTs, AXI4-Lite busses, etc.)
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- extensible set of macros
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- memory initialization file to facilitate code development without rebuilds
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- simulation diagnostics to facilitate identifying code errors
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- conditionally included I/Os and peripherals, functions, and assembly code
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SSBCC has been used for the following projects:
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SSBCC has been used for the following projects:
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- operate a media translator from a parallel camera interface to an OMAP GPMC
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- operate a media translator from a parallel camera interface to an OMAP GPMC
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interface, detect and report bus errors and hardware errors, and act as an
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interface, detect and report bus errors and hardware errors, and act as an
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SPI slave to the OMAP
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SPI slave to the OMAP
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- operate two UART interfaces and multiple PWM controlled 2-lead bi-color LEDs
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- operate two UART interfaces and multiple PWM controlled 2-lead bi-color LEDs
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- operate and monitor the Artix-7 fabric in a Zynq system using AXI4-Lite
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- operate and monitor the Artix-7 fabric in a Zynq system using AXI4-Lite
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master and slave buses, I2C buses for timing-critical voltage measurements
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master and slave buses, I2C buses for timing-critical voltage measurements
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The only external tool required is Python 2.7.
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DESCRIPTION
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DESCRIPTION
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================================================================================
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================================================================================
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The computer compiler uses an architectural description of the processor stating
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The computer compiler uses an architectural description of the processor stating
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the sizes of the instruction memory, data stack, and return stack; the input and
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the sizes of the instruction memory, data stack, and return stack; the input and
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output ports; RAM and ROM types and sizes; and peripherals.
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output ports; RAM and ROM types and sizes; and peripherals.
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The instructions are all single-cycle. The instructions include
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The instructions are all single-cycle. The instructions include
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- pushing an 8-bit value onto the data stack
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- 4 arithmetic instructions: addition, subtraction, increment, and decrement
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- arithmetic operations: addition, subtraction, increment, and decrement
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- 3 bit-wise logical instructions: and, or, and exclusive or
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- bit-wise logical operations: and, or, and exclusive or
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- 7 shift and rotation instructions: <<0, <<1, 0>>, 1>>, <>msb, and >>lsb
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- rotations
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- 4 logical instructions: 0=, 0<>, -1=, -1<>
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- logical operations: 0=, 0<>, -1=, -1<>
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- 6 Forth-like data stack instructions: drop, dup, nip, over, push, swap
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- Forth-like data stack operations: dup, over, swap, drop, nip
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- 3 Forth-like return stack instructions: >r, r>, r@
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- Forth-like return stack operations: >r, r>, r@
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- 2 input and output
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- input and output port operations
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- 6 memory read and write with optional address post increment and post decrement
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- memory read and write with optional address post increment and post decrement
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- 2 jump and conditional jump
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- jumps and conditional jumps
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- 2 call and conditional call
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- calls and conditional calls
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- 1 function return
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- function return
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- 1 nop
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The 9x8 address space is up to 8K. This is achieved by pushing the 8 lsb of the
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The 9x8 address space is up to 8K. This is achieved by pushing the 8 lsb of the
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target address onto the data stack immediately before the jump or call
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target address onto the data stack immediately before the jump or call
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instruction and by encoding the 5 msb of the address within the jump or call
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instruction and by encoding the 5 msb of the address within the jump or call
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instruction. The instruction immediately following a jump, call, or return is
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instruction. The instruction immediately following a jump, call, or return is
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(this is illustrated later).
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(this is illustrated later).
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Up to four banks of memory, either RAM or ROM, are available. Each of these can
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Up to four banks of memory, either RAM or ROM, are available. Each of these can
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be up to 256 bytes long, providing a total of up to 1 kB of memory.
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be up to 256 bytes long, providing a total of up to 1 kB of memory.
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The assembly language is Forth-like. Macros are used to encode the jump and
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The assembly language is Forth-like. Built-in macros are used to encode the
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call instructions and to encode the 2-bit memory bank index in memory store and
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jump and call instructions and to encode the 2-bit memory bank index in memory
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fetch instructions.
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store and fetch instructions.
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The computer compiler and assembler are written in Python 2.7. Peripherals are
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The computer compiler and assembler are written in Python 2.7. Peripherals are
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implemented by Python modules which generate the I/O ports and the peripheral
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implemented by Python modules which generate the I/O ports and the peripheral
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HDL.
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HDL.
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documented in the core/9x8/doc directory. Several examples are provided.
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documented in the core/9x8/doc directory. Several examples are provided.
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The computer compiler and assembler are fully functional and there are no known
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The computer compiler and assembler are fully functional and there are no known
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bugs.
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bugs.
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Features and peripherals are still being added and the documentation is
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incomplete. The output HDL is currently restricted to Verilog although a VHDL
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package file is automatically generated by the computer compiler.
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SPEED AND RESOURCE UTILIZATION
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SPEED AND RESOURCE UTILIZATION
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================================================================================
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================================================================================
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These device speed and resource utilization results are copied from the build
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These device speed and resource utilization results are copied from the build
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tests. The full results are listed in core/9x8/build/uc/uc_led.9x8 which
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tests. The full results are listed in core/9x8/build/uc/uc_led.9x8 which
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particularly with lots of I/O ports and peripherals and with the constraint of
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particularly with lots of I/O ports and peripherals and with the constraint of
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existing with other subsystems in the FPGA fabric. What these performance
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existing with other subsystems in the FPGA fabric. What these performance
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numbers do provide is an estimate of the amount of slack available. For
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numbers do provide is an estimate of the amount of slack available. For
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example, you can't realistically expect to get 110 MHz from a processor that,
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example, you can't realistically expect to get 110 MHz from a processor that,
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under ideal conditions, routes and places at 125 MHz, but you can with a
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under ideal conditions, routes and places at 125 MHz, but you can with a
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processor that synthesizes at more than 150 MHz.
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processor that synthesizes at 150 MHz.
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EXAMPLE:
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EXAMPLE:
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================================================================================
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================================================================================
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Forth uses counted strings, which are specified here as
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Forth uses counted strings, which are specified here as
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C"Hello World!"
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C"Hello World!"
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In this case the number of characters, 12 in this example, in the string is
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In this case the number of characters, 12, in the string is pushed onto the data
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pushed onto the data stack after the 'H', i.e., the instruction sequence would
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stack after the 'H', i.e., the instruction sequence would be
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be
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'!' 'd' 'l' ... 'e' 'H' 12
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'!' 'd' 'l' ... 'e' 'H' 12
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Finally, a lesser-counted string specified like
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Finally, a lesser-counted string specified like
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...
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...
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The following macros are provided in macros/9x8:
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The following macros are provided in macros/9x8:
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.push16(v) push the 16-bit (2-byte) value "v" onto the data stack with the
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.push16(v) push the 16-bit (2-byte) value "v" onto the data stack with the
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MSB at the top of the data stack
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MSB at the top of the data stack
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.push24(v) push the 24-bit (3-byte) value "v" onto the data stack with the
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MSB at the top of the data stack
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.push32(v) push the 32-bit (4-byte) value "v" onto the data stack with the
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.push32(v) push the 32-bit (4-byte) value "v" onto the data stack with the
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MSB at the top of the data stack
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MSB at the top of the data stack
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.pushByte(v,ix)
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push the ix'th byte of v onto the data stack
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Note: ix=0 designates the LSB
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Directories are searched in the following order for macros:
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Directories are searched in the following order for macros:
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./macros
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./macros
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include paths specified by the '-M' command line option.
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include paths specified by the '-M' command line option.
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The python scripts in core/9x8/macros and macros/9x8 can be used as design
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The python scripts in core/9x8/macros and macros/9x8 can be used as design
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examples for user-defined macros. The assembler does some type checking based
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examples for user-defined macros. The assembler does some type checking based
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on the list provided when the macro is registered by the "AddMacro" method, but
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on the list provided when the macro is registered by the "AddMacro" method, but
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additional type checking is often warranted by the macro "emitFunction" which
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additional type checking is often warranted by the macro "emitFunction" which
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emits the actual assembly code. The ".fetchvector" and ".storevector" macros
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emits the actual assembly code. The ".fetchvector" and ".storevector" macros
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demonstrates how to design variable-length macros.
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demonstrates how to design variable-length macros. Several macros in
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core/9x8/macros illustrate designing macros with optional arguments.
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It is not an error to repeat the ".macro MACRO_NAME" directive for user-defined
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It is not an error to repeat the ".macro MACRO_NAME" directive for user-defined
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macros. The assembler will issue a fatal error if a user-defined macro
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macros. The assembler will issue a fatal error if a user-defined macro
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conflicts with a built-in macro.
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conflicts with a built-in macro.
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MISCELLANEOUS
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MISCELLANEOUS
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================================================================================
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================================================================================
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Features and peripherals are still being added and the documentation is
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incomplete. The output HDL is currently restricted to Verilog although a VHDL
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package file is automatically generated by the computer compiler.
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The "INVERT_RESET" configuration command is used to indicate an active-low reset
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The "INVERT_RESET" configuration command is used to indicate an active-low reset
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is input to the micro controller rather than an active-high reset.
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is input to the micro controller rather than an active-high reset.
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A VHDL package file is automatically generated by the computer compiler.
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A VHDL package file is automatically generated by the computer compiler.
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