| Line 18... |
Line 18... |
I/Os, program memory, etc.
|
I/Os, program memory, etc.
|
|
|
The features are:
|
The features are:
|
- high speed, low fabric utilization
|
- high speed, low fabric utilization
|
- vendor-independent Verilog output with a VHDL package file
|
- vendor-independent Verilog output with a VHDL package file
|
- simple Forth-like assembly language (41 instructions)
|
- simple Forth-like assembly language (43 instructions)
|
- single cycle instruction execution
|
- single cycle instruction execution
|
- automatic generation of I/O ports
|
- automatic generation of I/O ports
|
- configurable instruction, data stack, return stack, and memory utilization
|
- configurable instruction, data stack, return stack, and memory utilization
|
- extensible set of peripherals (I2C busses, UARTs, AXI4-Lite busses, etc.)
|
- extensible set of peripherals (I2C busses, UARTs, AXI4-Lite busses, etc.)
|
- extensible set of macros
|
- extensible set of macros
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| Line 48... |
Line 48... |
the sizes of the instruction memory, data stack, and return stack; the input and
|
the sizes of the instruction memory, data stack, and return stack; the input and
|
output ports; RAM and ROM types and sizes; and peripherals.
|
output ports; RAM and ROM types and sizes; and peripherals.
|
|
|
The instructions are all single-cycle. The instructions include
|
The instructions are all single-cycle. The instructions include
|
- 4 arithmetic instructions: addition, subtraction, increment, and decrement
|
- 4 arithmetic instructions: addition, subtraction, increment, and decrement
|
|
- 2 carry bit instructions: +c and -c for addition and subtraction respectively
|
- 3 bit-wise logical instructions: and, or, and exclusive or
|
- 3 bit-wise logical instructions: and, or, and exclusive or
|
- 7 shift and rotation instructions: <<0, <<1, 0>>, 1>>, <>msb, and >>lsb
|
- 7 shift and rotation instructions: <<0, <<1, 0>>, 1>>, <>msb, and >>lsb
|
- 4 logical instructions: 0=, 0<>, -1=, -1<>
|
- 4 logical instructions: 0=, 0<>, -1=, -1<>
|
- 6 Forth-like data stack instructions: drop, dup, nip, over, push, swap
|
- 6 Forth-like data stack instructions: drop, dup, nip, over, push, swap
|
- 3 Forth-like return stack instructions: >r, r>, r@
|
- 3 Forth-like return stack instructions: >r, r>, r@
|
| Line 88... |
Line 89... |
|
|
|
|
SPEED AND RESOURCE UTILIZATION
|
SPEED AND RESOURCE UTILIZATION
|
================================================================================
|
================================================================================
|
These device speed and resource utilization results are copied from the build
|
These device speed and resource utilization results are copied from the build
|
tests. The full results are listed in core/9x8/build/uc/uc_led.9x8 which
|
tests. The full results are listed in the core/9x8/build directories. The
|
represents a minimal processor implementation (clock, reset, and one output).
|
tests use a minimal processor implementation (clock, reset, and one output).
|
See the uc_peripherals.9x8 file for results for a more complicated
|
Device-specific scripts state how these performance numbers were obtained.
|
implementation. Device-specific scripts state how these performance numbers
|
|
were obtained.
|
|
|
|
VENDOR DEVICE BEST SPEED SMALLEST RESOURCE UTILIZATION
|
VENDOR DEVICE BEST SPEED SMALLEST RESOURCE UTILIZATION
|
------ ------ ---------- -------------------------------
|
------ ------ ---------- -------------------------------
|
Altera Cyclone-III 190.6 MHz 282 LEs (preliminary)
|
Altera Cyclone-III 190.6 MHz 282 LEs (preliminary)
|
Altera Cyclone-IV 192.1 MHz 281 LEs (preliminary)
|
Altera Cyclone-IV 192.1 MHz 281 LEs (preliminary)
|
Altera Stratix-V 372.9 MHz 198 ALUTs (preliminary)
|
Altera Stratix-V 372.9 MHz 198 ALUTs (preliminary)
|
Lattice LCMXO2-640ZE-3 98.4 MHz 206 LUTs (preliminary)
|
Lattice LCMXO2-640ZE-3 98.4 MHz 206 LUTs (preliminary)
|
Lattice LFE2-6E-7 157.9 MHz 203 LUTs (preliminary)
|
Lattice LFE2-6E-7 157.9 MHz 203 LUTs (preliminary)
|
Xilinx Artix-7 316.5 MHz 151 slice LUTs (41 slices)
|
Xilinx Artix-7 TBD 163 slice LUTs (48 slices)
|
Xilinx Kintex-7 473.9 MHz 196 slice LUTs (55 slices)
|
Xilinx Kintex-7 TBD 158 slice LUTs (44 slices)
|
Xilinx Spartan-3A 148.3 MHz 231 4-input LUTs (130 slices)
|
Xilinx Spartan-3A 149.4 MHz 232 4-input LUTs (129 slices)
|
Xilinx Spartan-6 200.0 MHz 120 Slice LUTs (36 slices)
|
Xilinx Spartan-6 193.7 MHz 124 Slice LUTs (34 slices)
|
Xilinx Virtex-6 275.7 MHz 122 Slice LUTs (38 slices) (p.)
|
Xilinx Virtex-6 275.7 MHz 122 Slice LUTs (38 slices) (p.)
|
|
|
Disclaimer: Like other embedded processors, these are the maximum performance
|
Disclaimer: Like other embedded processors, these are the maximum performance
|
claims. Realistic implementations will produce slower maximum clock rates,
|
claims. Realistic implementations will produce slower maximum clock rates,
|
particularly with lots of I/O ports and peripherals and with the constraint of
|
particularly with lots of I/O ports and peripherals and with the constraint of
|
| Line 379... |
Line 378... |
|
|
|
|
INSTRUCTIONS
|
INSTRUCTIONS
|
================================================================================
|
================================================================================
|
|
|
The 41 instructions are as follows (see core/9x8/doc/opcodes.html for detailed
|
The 43 instructions are as follows (see core/9x8/doc/opcodes.html for detailed
|
descriptions). Here, T is the top of the data stack, N is the next-to-top of
|
descriptions). Here, T is the top of the data stack, N is the next-to-top of
|
the data stack, and R is the top of the return stack. All of these are the
|
the data stack, and R is the top of the return stack. All of these are the
|
values at the start of the instruction.
|
values at the start of the instruction.
|
|
|
The nop instruction does nothing:
|
The nop instruction does nothing:
|
| Line 397... |
Line 396... |
+ N + T
|
+ N + T
|
- N - T
|
- N - T
|
^ bitwise exclusive or of N and T
|
^ bitwise exclusive or of N and T
|
or bitwise or of N and T
|
or bitwise or of N and T
|
|
|
|
Push the carry bit for addition or subtraction onto the data stack (see
|
|
lib/9x8/math.s for examples on using +c and -c for multi-byte arithmetic):
|
|
|
|
+c carry bit for N+T
|
|
-c carry bit for N-T
|
|
|
Increment and decrement replace the top of the data stack with the stated
|
Increment and decrement replace the top of the data stack with the stated
|
result.
|
result.
|
|
|
1+ replace T with T+1
|
1+ replace T with T+1
|
1- replace T with T-1
|
1- replace T with T-1
|
