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Line 1... |
################################################################################
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################################################################################
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#
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#
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# Copyright 2013, Sinclair R.F., Inc.
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# Copyright 2013-2014, Sinclair R.F., Inc.
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#
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#
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################################################################################
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################################################################################
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import math
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import math
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import re;
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import re;
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| Line 199... |
Line 199... |
'error',
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'error',
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'synchronous',
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'synchronous',
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):
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):
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if not hasattr(self,paramname):
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if not hasattr(self,paramname):
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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# Ensure exclusive pair configurations are set and consistent.
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for exclusivepair in (
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('write_enable','noWSTRB',None,None,),
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):
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if hasattr(self,exclusivepair[0]) and hasattr(self,exclusivepair[1]):
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raise SSBCCException('Only one of "%s" and "%s" can be specified at %s' % (exclusivepair[0],exclusivepair[1],loc,));
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if not hasattr(self,exclusivepair[0]) and not hasattr(self,exclusivepair[1]) and exclusivepair[2]:
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setattr(self,exclusivepair[2],exclusivepair[3]);
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# Ensure one and only one of the complementary optional values are set.
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# Ensure one and only one of the complementary optional values are set.
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if not hasattr(self,'write_enable') and not hasattr(self,'noWSTRB'):
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if not hasattr(self,'write_enable') and not hasattr(self,'noWSTRB'):
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raise SSBCCException('One of "write_enable" or "noWSTRB" must be set at %s' % loc);
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raise SSBCCException('One of "write_enable" or "noWSTRB" must be set at %s' % loc);
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if hasattr(self,'write_enable') and hasattr(self,'noWSTRB'):
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raise SSBCCException('Only one of "write_enable" or "noWSTRB" can be set at %s' % loc);
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self.noWSTRB = hasattr(self,'noWSTRB');
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# Temporary: Warning message
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# Temporary: Warning message
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if not self.synchronous:
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if not self.synchronous:
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raise SSBCCException('synchronous=False has not been validated yet');
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raise SSBCCException('synchronous=False has not been validated yet');
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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for signal in (
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for signal in (
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( 'i_%s_aresetn', 1, 'input', ),
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( '%s_aresetn', 1, 'input', ),
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( 'i_%s_aclk', 1, 'input', ),
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( '%s_aclk', 1, 'input', ),
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( 'o_%s_awvalid', 1, 'output', ),
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( '%s_awvalid', 1, 'output', ),
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( 'i_%s_awready', 1, 'input', ),
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( '%s_awready', 1, 'input', ),
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( 'o_%s_awaddr', self.address_width, 'output', ),
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( '%s_awaddr', self.address_width, 'output', ),
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( 'o_%s_wvalid', 1, 'output', ),
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( '%s_wvalid', 1, 'output', ),
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( 'i_%s_wready', 1, 'input', ),
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( '%s_wready', 1, 'input', ),
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( 'o_%s_wdata', 32, 'output', ),
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( '%s_wdata', 32, 'output', ),
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( 'o_%s_wstrb', 4, 'output', ) if not self.noWSTRB else None,
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( '%s_wstrb', 4, 'output', ) if hasattr(self,'write_enable') else None,
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( 'i_%s_bresp', 2, 'input', ),
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( '%s_bresp', 2, 'input', ),
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( 'i_%s_bvalid', 1, 'input', ),
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( '%s_bvalid', 1, 'input', ),
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( 'o_%s_bready', 1, 'output', ),
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( '%s_bready', 1, 'output', ),
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( 'o_%s_arvalid', 1, 'output', ),
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( '%s_arvalid', 1, 'output', ),
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( 'i_%s_arready', 1, 'input', ),
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( '%s_arready', 1, 'input', ),
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( 'o_%s_araddr', self.address_width, 'output', ),
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( '%s_araddr', self.address_width, 'output', ),
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( 'i_%s_rvalid', 1, 'input', ),
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( '%s_rvalid', 1, 'input', ),
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( 'o_%s_rready', 1, 'output', ),
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( '%s_rready', 1, 'output', ),
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( 'i_%s_rdata', 32, 'input', ),
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( '%s_rdata', 32, 'input', ),
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( 'i_%s_rresp', 2, 'input', ),
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( '%s_rresp', 2, 'input', ),
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):
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):
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if not signal:
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if not signal:
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continue
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continue
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thisName = signal[0] % self.basePortName;
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thisName = signal[0] % self.basePortName;
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config.AddIO(thisName,signal[1],signal[2],loc);
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config.AddIO(thisName,signal[1],signal[2],loc);
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| Line 248... |
Line 253... |
),loc);
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),loc);
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self.ix_data = config.NOutports();
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self.ix_data = config.NOutports();
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config.AddOutport((self.data,False,
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config.AddOutport((self.data,False,
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# empty list -- disable normal output port signal generation
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# empty list -- disable normal output port signal generation
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),loc);
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),loc);
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if not self.noWSTRB:
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if hasattr(self,'write_enable'):
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config.AddOutport((self.write_enable,False,
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config.AddOutport((self.write_enable,False,
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('o_%s_wstrb' % self.basePortName, 4, 'data', ),
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('%s_wstrb' % self.basePortName, 4, 'data', ),
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),loc);
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),loc);
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config.AddOutport((self.command_read,True,
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config.AddOutport((self.command_read,True,
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('s__%s__rd' % self.basePortName, 1, 'strobe', ),
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('s__%s__rd' % self.basePortName, 1, 'strobe', ),
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),loc);
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),loc);
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config.AddOutport((self.command_write,True,
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config.AddOutport((self.command_write,True,
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| Line 276... |
Line 281... |
# avoid i_clk and i_rst
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# avoid i_clk and i_rst
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for subpair in (
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for subpair in (
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(r'\bgen__', 'gen__@NAME@__', ),
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(r'\bgen__', 'gen__@NAME@__', ),
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(r'\bL__', 'L__@NAME@__', ),
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(r'\bL__', 'L__@NAME@__', ),
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(r'\bs__', 's__@NAME@__', ),
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(r'\bs__', 's__@NAME@__', ),
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(r'\bi_a', 'i_@NAME@_a', ),
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( r'\bi_a', '@NAME@_a', ),
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(r'\bi_b', 'i_@NAME@_b', ),
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( r'\bi_b', '@NAME@_b', ),
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(r'\bi_rd', 'i_@NAME@_rd', ),
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( r'\bi_rd', '@NAME@_rd', ),
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(r'\bi_rr', 'i_@NAME@_rr', ),
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( r'\bi_rr', '@NAME@_rr', ),
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(r'\bi_rv', 'i_@NAME@_rv', ),
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( r'\bi_rv', '@NAME@_rv', ),
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(r'\bi_w', 'i_@NAME@_w', ),
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( r'\bi_w', '@NAME@_w', ),
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(r'\bo_', 'o_@NAME@_', ),
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( r'\bo_', '@NAME@_', ),
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(r'@ADDRESS_WIDTH@', str(self.address_width), ),
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(r'@ADDRESS_WIDTH@', str(self.address_width), ),
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(r'@ISSYNC@', "1'b1" if self.synchronous else "1'b0", ),
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(r'@ISSYNC@', "1'b1" if self.synchronous else "1'b0", ),
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(r'@IX_ADDRESS@', str(self.ix_address), ),
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(r'@IX_ADDRESS@', str(self.ix_address), ),
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(r'@IX_DATA@', str(self.ix_data), ),
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(r'@IX_DATA@', str(self.ix_data), ),
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(r'@IX_READ@', str(self.ix_read), ),
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(r'@IX_READ@', str(self.ix_read), ),
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| Line 294... |
Line 299... |
):
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):
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body = re.sub(subpair[0],subpair[1],body);
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body = re.sub(subpair[0],subpair[1],body);
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body = self.GenVerilogFinal(config,body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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fp.write(body);
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# Write the TCL script to facilitate creating Vivado IP for the port.
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vivadoFile = os.path.join(os.path.dirname(self.peripheralFile),'vivado_AXI4_Lite_Bus.py');
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execfile(vivadoFile,globals());
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WriteTclScript('master',self.basePortName,self.address_width,noWSTRB=self.noWSTRB);
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No newline at end of file
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No newline at end of file
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