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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [AXI4_Lite_Slave_DualPortRAM.py] - Diff between revs 6 and 9

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Rev 6 Rev 9
Line 102... Line 102...
      ( 'address',      r'O_\w+$',      None,           ),
      ( 'address',      r'O_\w+$',      None,           ),
      ( 'basePortName', r'\w+$',        None,           ),
      ( 'basePortName', r'\w+$',        None,           ),
      ( 'ram8',         None,           None,           ),
      ( 'ram8',         None,           None,           ),
      ( 'ram32',        None,           None,           ),
      ( 'ram32',        None,           None,           ),
      ( 'read',         r'I_\w+$',      None,           ),
      ( 'read',         r'I_\w+$',      None,           ),
      ( 'size',         r'\S+$',        lambda v : self.FixedPow2(config,16,256,v), ),
      ( 'size',         r'\S+$',        lambda v : self.IntPow2Method(config,v,lowLimit=16,highLimit=256), ),
      ( 'write',        r'O_\w+$',      None,           ),
      ( 'write',        r'O_\w+$',      None,           ),
    );
    );
    names = [a[0] for a in allowables];
    names = [a[0] for a in allowables];
    for param_tuple in param_list:
    for param_tuple in param_list:
      param = param_tuple[0];
      param = param_tuple[0];

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