| Line 45... |
Line 45... |
ram8
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ram8
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optionally specifies using an 8-bit RAM for the dual-port memory instantiation
|
optionally specifies using an 8-bit RAM for the dual-port memory instantiation
|
Note: This is the default
|
Note: This is the default
|
ram32
|
ram32
|
optionally specifies using a 32-bit RAM for the dual-port memrory instantiation
|
optionally specifies using a 32-bit RAM for the dual-port memrory instantiation
|
Note: This is required for Vivado 2013.3.
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Note: This is required for Vivado 2013.3.\n
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|
Vivado Users:
|
|
The peripheral creates a TCL script to facilitate turning the micro
|
|
controller into an IP core. Look for a file with the name
|
|
"vivado_<basePortName>.tcl".\n
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Example: The code fragments
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Example: The code fragments
|
<addr> .outport(O_address) .inport(I_read)
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<addr> .outport(O_address) .inport(I_read)
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and
|
and
|
<addr> .outport(O_address) <value> .outport(O_write)
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<addr> .outport(O_address) <value> .outport(O_write)
|
will read from and write to the dual-port RAM.\n
|
will read from and write to the dual-port RAM.\n
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| Line 152... |
Line 156... |
if not hasattr(self,exclusivepair[0]) and not hasattr(self,exclusivepair[1]):
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if not hasattr(self,exclusivepair[0]) and not hasattr(self,exclusivepair[1]):
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setattr(self,exclusivepair[2],exclusivepair[3]);
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setattr(self,exclusivepair[2],exclusivepair[3]);
|
# Set the string used to identify signals associated with this peripheral.
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# Set the string used to identify signals associated with this peripheral.
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self.namestring = self.basePortName;
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self.namestring = self.basePortName;
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
|
|
self.address_width = int(math.log(self.size,2));
|
for signal in (
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for signal in (
|
( 'i_%s_aresetn', 1, 'input', ),
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( 'i_%s_aresetn', 1, 'input', ),
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( 'i_%s_aclk', 1, 'input', ),
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( 'i_%s_aclk', 1, 'input', ),
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( 'i_%s_awvalid', 1, 'input', ),
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( 'i_%s_awvalid', 1, 'input', ),
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( 'o_%s_awready', 1, 'output', ),
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( 'o_%s_awready', 1, 'output', ),
|
( 'i_%s_awaddr', math.log(self.size,2), 'input', ),
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( 'i_%s_awaddr', self.address_width, 'input', ),
|
( 'i_%s_wvalid', 1, 'input', ),
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( 'i_%s_wvalid', 1, 'input', ),
|
( 'o_%s_wready', 1, 'output', ),
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( 'o_%s_wready', 1, 'output', ),
|
( 'i_%s_wdata', 32, 'input', ),
|
( 'i_%s_wdata', 32, 'input', ),
|
( 'i_%s_wstrb', 4, 'input', ),
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( 'i_%s_wstrb', 4, 'input', ),
|
( 'o_%s_bresp', 2, 'output', ),
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( 'o_%s_bresp', 2, 'output', ),
|
( 'o_%s_bvalid', 1, 'output', ),
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( 'o_%s_bvalid', 1, 'output', ),
|
( 'i_%s_bready', 1, 'input', ),
|
( 'i_%s_bready', 1, 'input', ),
|
( 'i_%s_arvalid', 1, 'input', ),
|
( 'i_%s_arvalid', 1, 'input', ),
|
( 'o_%s_arready', 1, 'output', ),
|
( 'o_%s_arready', 1, 'output', ),
|
( 'i_%s_araddr', math.log(self.size,2), 'input', ),
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( 'i_%s_araddr', self.address_width, 'input', ),
|
( 'o_%s_rvalid', 1, 'output', ),
|
( 'o_%s_rvalid', 1, 'output', ),
|
( 'i_%s_rready', 1, 'input', ),
|
( 'i_%s_rready', 1, 'input', ),
|
( 'o_%s_rdata', 32, 'output', ),
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( 'o_%s_rdata', 32, 'output', ),
|
( 'o_%s_rresp', 2, 'output', ),
|
( 'o_%s_rresp', 2, 'output', ),
|
):
|
):
|
thisName = signal[0] % self.basePortName;
|
thisName = signal[0] % self.basePortName;
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config.AddIO(thisName,signal[1],signal[2],loc);
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config.AddIO(thisName,signal[1],signal[2],loc);
|
config.AddSignal('s__%s__mc_addr' % self.namestring, int(math.log(self.size,2)), loc);
|
config.AddSignal('s__%s__mc_addr' % self.namestring, self.address_width, loc);
|
config.AddSignal('s__%s__mc_rdata' % self.namestring, 8, loc);
|
config.AddSignal('s__%s__mc_rdata' % self.namestring, 8, loc);
|
config.AddOutport((self.address,False,
|
config.AddOutport((self.address,False,
|
('s__%s__mc_addr' % self.namestring, int(math.log(self.size,2)), 'data', ),
|
('s__%s__mc_addr' % self.namestring, self.address_width, 'data', ),
|
),loc);
|
),loc);
|
config.AddInport((self.read,
|
config.AddInport((self.read,
|
('s__%s__mc_rdata' % self.namestring, 8, 'data', ),
|
('s__%s__mc_rdata' % self.namestring, 8, 'data', ),
|
),loc);
|
),loc);
|
self.ix_write = config.NOutports();
|
self.ix_write = config.NOutports();
|
| Line 211... |
Line 216... |
):
|
):
|
body = re.sub(subpair[0],subpair[1],body);
|
body = re.sub(subpair[0],subpair[1],body);
|
body = self.GenVerilogFinal(config,body);
|
body = self.GenVerilogFinal(config,body);
|
fp.write(body);
|
fp.write(body);
|
|
|
No newline at end of file
|
No newline at end of file
|
|
# Write the TCL script to facilitate creating Vivado IP for the port.
|
|
vivadoFile = os.path.join(os.path.dirname(self.peripheralFile),'vivado_AXI4_Lite_Bus.py');
|
|
execfile(vivadoFile,globals());
|
|
WriteTclScript('slave',self.basePortName,self.address_width);
|
|
|
No newline at end of file
|
No newline at end of file
|
