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Line 1... |
################################################################################
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################################################################################
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#
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#
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# Copyright 2013, Sinclair R.F., Inc.
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# Copyright 2013-2014, Sinclair R.F., Inc.
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#
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#
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################################################################################
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################################################################################
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|
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import math
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import math
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import re;
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import re;
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| Line 96... |
Line 96... |
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def __init__(self,peripheralFile,config,param_list,loc):
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def __init__(self,peripheralFile,config,param_list,loc):
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# Use the externally provided file name for the peripheral
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# Use the externally provided file name for the peripheral
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self.peripheralFile = peripheralFile;
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self.peripheralFile = peripheralFile;
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# Get the parameters.
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# Get the parameters.
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def validateSize(x):
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if re.match(r'L_\w+$',x):
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if not config.IsParameter(x):
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raise SSBCCException('"size=%s" is not a parameter at %s' % (x,loc,));
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ix = [param[0] for param in config.parameters].index(x);
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y = config.parameters[ix][1];
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if not re.match(r'[1-9]\d*$', y):
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raise SSBCCException('localparam must be a numeric constant, not "%s", to be used in "size=%s" at %s' % (y,x,loc,));
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y = int(y);
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elif re.match(r'C_\w+$',x):
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if not config.IsConstant(x):
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raise SSBCCException('"size=%s" is not a constant at %s' % (x,loc,));
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y = int(config.constants[x]);
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elif re.match(r'[1-9]\d*$',x):
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y = int(x);
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else:
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raise SSBCCException('Malformed entry for "size=%s" at %s' % (x,loc,));
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if math.modf(math.log(y,2))[0] != 0:
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raise SSBCCException('size=%d must be a power of 2 at %s' % (y,loc,));
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if not (16 <= y <= 256):
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raise SSBCCException('size=%d must be between 16 and 256 inclusive at %s' % (y,loc,));
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return y;
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allowables = (
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allowables = (
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('address', r'O_\w+$', None, ),
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('address', r'O_\w+$', None, ),
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('basePortName', r'\w+$', None, ),
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('basePortName', r'\w+$', None, ),
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('ram8', None, None, ),
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('ram8', None, None, ),
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('ram32', None, None, ),
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('ram32', None, None, ),
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('read', r'I_\w+$', None, ),
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('read', r'I_\w+$', None, ),
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('size', r'\S+$', validateSize, ),
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( 'size', r'\S+$', lambda v : self.FixedPow2(config,16,256,v), ),
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('write', r'O_\w+$', None, ),
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('write', r'O_\w+$', None, ),
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);
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);
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names = [a[0] for a in allowables];
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names = [a[0] for a in allowables];
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for param_tuple in param_list:
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for param_tuple in param_list:
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param = param_tuple[0];
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param = param_tuple[0];
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| Line 162... |
Line 140... |
# Set the string used to identify signals associated with this peripheral.
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# Set the string used to identify signals associated with this peripheral.
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self.namestring = self.basePortName;
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self.namestring = self.basePortName;
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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self.address_width = int(math.log(self.size,2));
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self.address_width = int(math.log(self.size,2));
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for signal in (
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for signal in (
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( 'i_%s_aresetn', 1, 'input', ),
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( '%s_aresetn', 1, 'input', ),
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( 'i_%s_aclk', 1, 'input', ),
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( '%s_aclk', 1, 'input', ),
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( 'i_%s_awvalid', 1, 'input', ),
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( '%s_awvalid', 1, 'input', ),
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( 'o_%s_awready', 1, 'output', ),
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( '%s_awready', 1, 'output', ),
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( 'i_%s_awaddr', self.address_width, 'input', ),
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( '%s_awaddr', self.address_width, 'input', ),
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( 'i_%s_wvalid', 1, 'input', ),
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( '%s_wvalid', 1, 'input', ),
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( 'o_%s_wready', 1, 'output', ),
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( '%s_wready', 1, 'output', ),
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( 'i_%s_wdata', 32, 'input', ),
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( '%s_wdata', 32, 'input', ),
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( 'i_%s_wstrb', 4, 'input', ),
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( '%s_wstrb', 4, 'input', ),
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( 'o_%s_bresp', 2, 'output', ),
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( '%s_bresp', 2, 'output', ),
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( 'o_%s_bvalid', 1, 'output', ),
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( '%s_bvalid', 1, 'output', ),
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( 'i_%s_bready', 1, 'input', ),
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( '%s_bready', 1, 'input', ),
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( 'i_%s_arvalid', 1, 'input', ),
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( '%s_arvalid', 1, 'input', ),
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( 'o_%s_arready', 1, 'output', ),
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( '%s_arready', 1, 'output', ),
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( 'i_%s_araddr', self.address_width, 'input', ),
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( '%s_araddr', self.address_width, 'input', ),
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( 'o_%s_rvalid', 1, 'output', ),
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( '%s_rvalid', 1, 'output', ),
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( 'i_%s_rready', 1, 'input', ),
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( '%s_rready', 1, 'input', ),
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( 'o_%s_rdata', 32, 'output', ),
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( '%s_rdata', 32, 'output', ),
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( 'o_%s_rresp', 2, 'output', ),
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( '%s_rresp', 2, 'output', ),
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):
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):
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thisName = signal[0] % self.basePortName;
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thisName = signal[0] % self.basePortName;
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config.AddIO(thisName,signal[1],signal[2],loc);
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config.AddIO(thisName,signal[1],signal[2],loc);
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config.AddSignal('s__%s__mc_addr' % self.namestring, self.address_width, loc);
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config.AddSignal('s__%s__mc_addr' % self.namestring, self.address_width, loc);
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config.AddSignal('s__%s__mc_rdata' % self.namestring, 8, loc);
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config.AddSignal('s__%s__mc_rdata' % self.namestring, 8, loc);
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| Line 204... |
Line 182... |
def GenVerilog(self,fp,config):
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def GenVerilog(self,fp,config):
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body = self.LoadCore(self.peripheralFile,'.v');
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body = self.LoadCore(self.peripheralFile,'.v');
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for subpair in (
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for subpair in (
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(r'\bL__', 'L__@NAME@__', ),
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(r'\bL__', 'L__@NAME@__', ),
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(r'\bgen__', 'gen__@NAME@__', ),
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(r'\bgen__', 'gen__@NAME@__', ),
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(r'\bi_a', 'i_@NAME@_a', ),
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( r'\bi_a', '@NAME@_a', ),
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(r'\bi_b', 'i_@NAME@_b', ),
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( r'\bi_b', '@NAME@_b', ),
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(r'\bi_r', 'i_@NAME@_r', ),
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( r'\bi_r', '@NAME@_r', ),
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(r'\bi_w', 'i_@NAME@_w', ),
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( r'\bi_w', '@NAME@_w', ),
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(r'\bix__', 'ix__@NAME@__', ),
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(r'\bix__', 'ix__@NAME@__', ),
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(r'\bo_', 'o_@NAME@_', ),
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( r'\bo_', '@NAME@_', ),
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(r'\bs__', 's__@NAME@__', ),
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(r'\bs__', 's__@NAME@__', ),
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(r'@IX_WRITE@', "8'h%02x" % self.ix_write, ),
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(r'@IX_WRITE@', "8'h%02x" % self.ix_write, ),
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(r'@NAME@', self.namestring, ),
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(r'@NAME@', self.namestring, ),
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(r'@SIZE@', str(self.size), ),
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(r'@SIZE@', str(self.size), ),
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(r'@MEM8@', '1' if hasattr(self,'mem8') else '0', ),
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(r'@MEM8@', '1' if hasattr(self,'mem8') else '0', ),
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):
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):
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body = re.sub(subpair[0],subpair[1],body);
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body = re.sub(subpair[0],subpair[1],body);
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body = self.GenVerilogFinal(config,body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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fp.write(body);
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# Write the TCL script to facilitate creating Vivado IP for the port.
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vivadoFile = os.path.join(os.path.dirname(self.peripheralFile),'vivado_AXI4_Lite_Bus.py');
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execfile(vivadoFile,globals());
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WriteTclScript('slave',self.basePortName,self.address_width);
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No newline at end of file
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No newline at end of file
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