URL
https://opencores.org/ocsvn/ssbcc/ssbcc/trunk
[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [AXI4_Lite_Slave_DualPortRAM.v] - Diff between revs 4 and 10
Show entire file |
Details |
Blame |
View Log
| Rev 4 |
Rev 10 |
| Line 1... |
Line 1... |
//
|
//
|
// PERIPHERAL: AXI4-Lite slave dual-port-RAM interface
|
// PERIPHERAL: AXI4-Lite slave dual-port-RAM interface
|
|
// Copyright 2014, Sinclair R.F., Inc.
|
//
|
//
|
// Note: While the AXI4-Lite protocol allows simultaneous read and write
|
// Note: While the AXI4-Lite protocol allows simultaneous read and write
|
// operations, only one side of the dual-port RAM is available to the AXI4-lite
|
// operations, only one side of the dual-port RAM is available to the AXI4-lite
|
// interface. This requires internal arbitration between the two operations
|
// interface. This requires internal arbitration between the two operations
|
// with either the first or the write operation being preferred.
|
// with either the first or the write operation being preferred.
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.