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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [AXI4_Lite_Slave_DualPortRAM.v] - Diff between revs 4 and 10
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//
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//
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// PERIPHERAL: AXI4-Lite slave dual-port-RAM interface
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// PERIPHERAL: AXI4-Lite slave dual-port-RAM interface
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// Copyright 2014, Sinclair R.F., Inc.
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//
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//
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// Note: While the AXI4-Lite protocol allows simultaneous read and write
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// Note: While the AXI4-Lite protocol allows simultaneous read and write
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// operations, only one side of the dual-port RAM is available to the AXI4-lite
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// operations, only one side of the dual-port RAM is available to the AXI4-lite
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// interface. This requires internal arbitration between the two operations
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// interface. This requires internal arbitration between the two operations
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// with either the first or the write operation being preferred.
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// with either the first or the write operation being preferred.
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