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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [AXI4_Lite_Slave_DualPortRAM.v] - Diff between revs 4 and 10

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//
//
// PERIPHERAL:  AXI4-Lite slave dual-port-RAM interface
// PERIPHERAL:  AXI4-Lite slave dual-port-RAM interface
 
// Copyright 2014, Sinclair R.F., Inc.
//
//
// Note:  While the AXI4-Lite protocol allows simultaneous read and write
// Note:  While the AXI4-Lite protocol allows simultaneous read and write
// operations, only one side of the dual-port RAM is available to the AXI4-lite
// operations, only one side of the dual-port RAM is available to the AXI4-lite
// interface.  This requires internal arbitration between the two operations
// interface.  This requires internal arbitration between the two operations
// with either the first or the write operation being preferred.
// with either the first or the write operation being preferred.

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