Line 24... |
Line 24... |
reg s__axi_idle = 1'b1;
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reg s__axi_idle = 1'b1;
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reg s__axi_got_waddr = 1'b0;
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reg s__axi_got_waddr = 1'b0;
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reg s__axi_got_wdata = 1'b0;
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reg s__axi_got_wdata = 1'b0;
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reg s__axi_got_raddr = 1'b0;
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reg s__axi_got_raddr = 1'b0;
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reg [L__NBITS_SIZE-1:2] s__axi_addr = {(L__NBITS_SIZE-2){1'b0}};
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reg [L__NBITS_SIZE-1:2] s__axi_addr = {(L__NBITS_SIZE-2){1'b0}};
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initial o_awready = 1'b0;
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initial o_wready = 1'b0;
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initial o_arready = 1'b0;
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always @ (posedge i_aclk)
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always @ (posedge i_aclk)
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if (~i_aresetn) begin
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if (~i_aresetn) begin
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s__axi_idle <= 1'b1;
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s__axi_idle <= 1'b1;
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s__axi_got_waddr <= 1'b0;
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s__axi_got_waddr <= 1'b0;
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s__axi_got_wdata <= 1'b0;
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s__axi_got_wdata <= 1'b0;
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s__axi_got_raddr <= 1'b0;
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s__axi_got_raddr <= 1'b0;
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s__axi_addr <= {(L__NBITS_SIZE-2){1'b0}};
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s__axi_addr <= {(L__NBITS_SIZE-2){1'b0}};
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o_awready <= 1'b0;
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o_wready <= 1'b0;
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o_arready <= 1'b0;
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end else begin
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end else begin
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s__axi_idle <= s__axi_idle;
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s__axi_idle <= s__axi_idle;
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s__axi_got_waddr <= s__axi_got_waddr;
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s__axi_got_waddr <= s__axi_got_waddr;
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s__axi_got_wdata <= s__axi_got_wdata;
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s__axi_got_wdata <= s__axi_got_wdata;
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s__axi_got_raddr <= s__axi_got_raddr;
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s__axi_got_raddr <= s__axi_got_raddr;
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Line 73... |
Line 79... |
end
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end
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end
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end
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initial o_bvalid = 1'b0;
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initial o_bvalid = 1'b0;
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always @ (*)
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always @ (*)
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o_bvalid = s__axi_got_wdata;
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o_bvalid = s__axi_got_wdata;
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reg s__axi_arready_s = 1'b0;
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always @ (posedge i_aclk)
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if (~i_aresetn)
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s__axi_arready_s <= 1'b0;
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else
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s__axi_arready_s <= o_arready;
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initial o_rvalid = 1'b0;
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initial o_rvalid = 1'b0;
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always @ (s__axi_got_raddr)
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always @ (posedge i_aclk)
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o_rvalid = s__axi_got_raddr;
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if (~i_aresetn)
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o_rvalid <= 1'b0;
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else if (s__axi_arready_s)
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o_rvalid <= 1'b1;
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else if (i_rready)
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o_rvalid <= 1'b0;
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else
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o_rvalid <= o_rvalid;
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// signals common to both memory architectures
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// signals common to both memory architectures
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reg [L__NBITS_SIZE-1:2] s__axi_addr_s = {(L__NBITS_SIZE-2){1'b0}};
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reg [L__NBITS_SIZE-1:2] s__axi_addr_s = {(L__NBITS_SIZE-2){1'b0}};
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always @ (posedge i_aclk)
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always @ (posedge i_aclk)
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s__axi_addr_s <= s__axi_addr;
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s__axi_addr_s <= s__axi_addr;
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reg [3:0] s__wstrb = 4'd0;
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reg [3:0] s__wstrb = 4'd0;
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