| Line 1... |
Line 1... |
################################################################################
|
################################################################################
|
#
|
#
|
# Copyright 2013-2014, Sinclair R.F., Inc.
|
# Copyright 2013-2015, Sinclair R.F., Inc.
|
#
|
#
|
################################################################################
|
################################################################################
|
|
|
import math;
|
import math;
|
import re;
|
import re;
|
|
|
from ssbccPeripheral import SSBCCperipheral
|
from ssbccPeripheral import SSBCCperipheral
|
from ssbccUtil import IsPowerOf2;
|
from ssbccUtil import CeilLog2
|
from ssbccUtil import SSBCCException;
|
from ssbccUtil import SSBCCException
|
|
|
class UART(SSBCCperipheral):
|
class UART(SSBCCperipheral):
|
"""
|
"""
|
Transmit/receive UART:
|
Transmit/receive UART:
|
1 start bit
|
1 start bit
|
| Line 28... |
Line 28... |
[noSync|sync=n] \\
|
[noSync|sync=n] \\
|
[noDeglitch|deglitch=n] \\
|
[noDeglitch|deglitch=n] \\
|
[noInFIFO|inFIFO=n] \\
|
[noInFIFO|inFIFO=n] \\
|
[noOutFIFO|outFIFO=n] \\
|
[noOutFIFO|outFIFO=n] \\
|
[{CTS|CTSn}=i_cts_name] \\
|
[{CTS|CTSn}=i_cts_name] \\
|
[{RTR|RTRn}=i_rtr_name] \\
|
[{RTR|RTRn}=o_rtr_name] \\
|
|
rtr_buffer=n \\
|
[nStop={1|2}]\n
|
[nStop={1|2}]\n
|
Where:
|
Where:
|
inport=I_inport_name
|
inport=I_inport_name
|
specifies the symbol used by the inport instruction to read a received by
|
specifies the symbol used by the inport instruction to read a received by
|
from the peripheral
|
from the peripheral
|
| Line 52... |
Line 53... |
baudmethod
|
baudmethod
|
specifies the method to generate the desired bit rate:
|
specifies the method to generate the desired bit rate:
|
1st method: clk/rate
|
1st method: clk/rate
|
clk is the frequency of "i_clk" in Hz
|
clk is the frequency of "i_clk" in Hz
|
a number will be interpreted as the clock frequency in Hz
|
a number will be interpreted as the clock frequency in Hz
|
a symbol will be interpreted as a parameter
|
a symbol will be interpreted as a constant or a parameter
|
Note: this parameter must have been declared with a "PARAMETER"
|
Note: the symbol must be declared with the CONSTANT, LOCALPARARM,
|
command
|
or PARAMETER configuration command.
|
rate is the desired baud rate
|
rate is the desired baud rate
|
this is specified as per "clk"
|
this is specified as per "clk"
|
2nd method:
|
2nd method:
|
specify the number of "i_clk" clock cycles between bit edges
|
specify the number of "i_clk" clock cycles between bit edges
|
Note: clk, rate, and count can be parameters or constants. For example,
|
Note: clk, rate, and count can be parameters or constants. For example,
|
| Line 108... |
Line 109... |
Note: The default, i.e., neither CTS nor CTSn is specified, is to always
|
Note: The default, i.e., neither CTS nor CTSn is specified, is to always
|
enable the transmitter.
|
enable the transmitter.
|
Note: If there is no FIFO and the CTS/CTSn handshake indicates that the
|
Note: If there is no FIFO and the CTS/CTSn handshake indicates that the
|
data flow is disabled, then the busy signal will be high and the
|
data flow is disabled, then the busy signal will be high and the
|
processor code must not transmit the next byte.
|
processor code must not transmit the next byte.
|
RTR=i_rtr_name or RTRn=i_rtr_name
|
RTR=o_rtr_name or RTRn=o_rtr_name
|
optionally specify an output handshake signal to indicate that the
|
optionally specify an output handshake signal to indicate that the
|
peripheral is ready to receive data
|
peripheral is ready to receive data
|
Note: If RTR is specified then the receiver indicates it is ready when
|
Note: If RTR is specified then the receiver indicates it is ready when
|
i_rtr_name is high. If RTRn is specified then the transmitter
|
o_rtr_name is high. If RTRn is specified then the transmitter
|
indicates it is ready when i_rtr_name is low.
|
indicates it is ready when o_rtr_name is low.
|
Note: The default, i.e., neither CTS nor CTSn is specified, is to always
|
Note: The default, i.e., neither CTS nor CTSn is specified, is to always
|
enable the receiver.
|
enable the receiver.
|
Note: If there is no FIFO and the RTR/RTRn handshake indicates that the
|
Note: If there is no FIFO and the RTR/RTRn handshake indicates that the
|
receiver is not ready as soon as it starts receiving data and
|
receiver is not ready as soon as it starts receiving data and
|
until that data is read from the peripheral.
|
until that data is read from the peripheral.
|
|
rtr_buffer=n
|
|
optionally specify the number of entries in inFIFO to reserve for data
|
|
received after the RTR/RTRn signal indicates to stop data flow.
|
|
Note: n must be a power of 2.
|
|
Note: This requires that inFIFO be specified.
|
|
Note: Some USB UARTs will transmit several characters after the RTR/RTRn
|
|
signal indicates to stop the data flow.
|
nStop=n
|
nStop=n
|
optionally configure the peripheral for n stop bits
|
optionally configure the peripheral for n stop bits
|
default: 1 stop bit
|
default: 1 stop bit
|
Note: n must be 1 or 2
|
Note: n must be 1 or 2
|
Note: the peripheral does not accept 1.5 stop bits\n
|
Note: the peripheral does not accept 1.5 stop bits\n
|
| Line 183... |
Line 191... |
( 'CTSn', r'i_\w+$', None, ),
|
( 'CTSn', r'i_\w+$', None, ),
|
( 'RTR', r'o_\w+$', None, ),
|
( 'RTR', r'o_\w+$', None, ),
|
( 'RTRn', r'o_\w+$', None, ),
|
( 'RTRn', r'o_\w+$', None, ),
|
( 'baudmethod', r'\S+$', lambda v : self.RateMethod(config,v), ),
|
( 'baudmethod', r'\S+$', lambda v : self.RateMethod(config,v), ),
|
( 'deglitch', r'[1-9]\d*$', int, ),
|
( 'deglitch', r'[1-9]\d*$', int, ),
|
( 'inFIFO', r'[1-9]\d*$', lambda v : self.IntPow2(v), ),
|
( 'inFIFO', r'[1-9]\d*$', lambda v : self.IntPow2Method(config,v), ),
|
( 'inempty', r'I_\w+$', None, ),
|
( 'inempty', r'I_\w+$', None, ),
|
( 'inport', r'I_\w+$', None, ),
|
( 'inport', r'I_\w+$', None, ),
|
( 'insignal', r'i_\w+$', None, ),
|
( 'insignal', r'i_\w+$', None, ),
|
( 'noDeglitch', None, None, ),
|
( 'noDeglitch', None, None, ),
|
( 'noInFIFO', None, None, ),
|
( 'noInFIFO', None, None, ),
|
( 'noOutFIFO', None, None, ),
|
( 'noOutFIFO', None, None, ),
|
( 'noSync', None, None, ),
|
( 'noSync', None, None, ),
|
( 'nStop', r'[12]$', int, ),
|
( 'nStop', r'[12]$', int, ),
|
( 'outFIFO', r'[1-9]\d*$', lambda v : self.IntPow2(v), ),
|
( 'outFIFO', r'[1-9]\d*$', lambda v : self.IntPow2Method(config,v), ),
|
( 'outport', r'O_\w+$', None, ),
|
( 'outport', r'O_\w+$', None, ),
|
( 'outsignal', r'o_\w+$', None, ),
|
( 'outsignal', r'o_\w+$', None, ),
|
( 'outstatus', r'I_\w+$', None, ),
|
( 'outstatus', r'I_\w+$', None, ),
|
|
( 'rtr_buffer', r'[1-9]\d*$', lambda v : self.IntPow2Method(config,v), ),
|
( 'sync', r'[1-9]\d*$', int, ),
|
( 'sync', r'[1-9]\d*$', int, ),
|
);
|
);
|
names = [a[0] for a in allowables];
|
names = [a[0] for a in allowables];
|
for param_tuple in param_list:
|
for param_tuple in param_list:
|
param = param_tuple[0];
|
param = param_tuple[0];
|
| Line 223... |
Line 232... |
( 'nStop', 1, ),
|
( 'nStop', 1, ),
|
( 'outsignal', 'o_UART_Tx', ),
|
( 'outsignal', 'o_UART_Tx', ),
|
):
|
):
|
if not hasattr(self,optionalpair[0]):
|
if not hasattr(self,optionalpair[0]):
|
setattr(self,optionalpair[0],optionalpair[1]);
|
setattr(self,optionalpair[0],optionalpair[1]);
|
# Ensure exclusive pair configurations are set and consistent.
|
# Ensure the rtr_buffer, if specified, is consistent with the inFIFO
|
|
# specification.
|
|
if hasattr(self,'rtr_buffer'):
|
|
if not hasattr(self,'inFIFO'):
|
|
raise SSBCCException('rtr_buffer specification requires simultaneous inFIFO specification at %s' % loc);
|
|
if self.rtr_buffer > self.inFIFO:
|
|
raise SSBCCException('rtr_buffer=%d specification cannot exceed inFIFO=%d specification at %s' % (self.rtr_buffer,self.inFIFO,loc,));
|
|
else:
|
|
self.rtr_buffer = 1;
|
|
# Ensure optional exclusive pair configurations are set and consistent.
|
for exclusivepair in (
|
for exclusivepair in (
|
( 'CTS', 'CTSn', None, None, ),
|
( 'CTS', 'CTSn', None, None, ),
|
( 'RTR', 'RTRn', None, None, ),
|
( 'RTR', 'RTRn', None, None, ),
|
( 'noSync', 'sync', 'sync', 3, ),
|
( 'noSync', 'sync', 'sync', 3, ),
|
( 'noDeglitch', 'deglitch', 'noDeglitch', True, ),
|
( 'noDeglitch', 'deglitch', 'noDeglitch', True, ),
|
| Line 262... |
Line 280... |
if hasattr(self,ioEntry[0]):
|
if hasattr(self,ioEntry[0]):
|
config.AddIO(getattr(self,ioEntry[0]),ioEntry[1],ioEntry[2],loc);
|
config.AddIO(getattr(self,ioEntry[0]),ioEntry[1],ioEntry[2],loc);
|
config.AddSignal('s__%s__Rx' % self.namestring,8,loc);
|
config.AddSignal('s__%s__Rx' % self.namestring,8,loc);
|
config.AddSignal('s__%s__Rx_empty' % self.namestring,1,loc);
|
config.AddSignal('s__%s__Rx_empty' % self.namestring,1,loc);
|
config.AddSignal('s__%s__Rx_rd' % self.namestring,1,loc);
|
config.AddSignal('s__%s__Rx_rd' % self.namestring,1,loc);
|
config.AddSignal('s__%s__Tx' % self.namestring,8,loc);
|
config.AddSignalWithInit('s__%s__Tx' % self.namestring,8,None,loc);
|
config.AddSignal('s__%s__Tx_busy' % self.namestring,1,loc);
|
config.AddSignal('s__%s__Tx_busy' % self.namestring,1,loc);
|
config.AddSignal('s__%s__Tx_wr' % self.namestring,1,loc);
|
config.AddSignalWithInit('s__%s__Tx_wr' % self.namestring,1,None,loc);
|
config.AddInport((self.inport,
|
config.AddInport((self.inport,
|
('s__%s__Rx' % self.namestring,8,'data',),
|
('s__%s__Rx' % self.namestring,8,'data',),
|
('s__%s__Rx_rd' % self.namestring,1,'strobe',),
|
('s__%s__Rx_rd' % self.namestring,1,'strobe',),
|
),loc);
|
),loc);
|
config.AddInport((self.inempty,
|
config.AddInport((self.inempty,
|
| Line 293... |
Line 311... |
else:
|
else:
|
if re.search(r'@RTR_BEGIN@',body):
|
if re.search(r'@RTR_BEGIN@',body):
|
body = re.sub(r'@RTR_BEGIN@.*?@RTR_END@\n','',body,flags=re.DOTALL);
|
body = re.sub(r'@RTR_BEGIN@.*?@RTR_END@\n','',body,flags=re.DOTALL);
|
for subpair in (
|
for subpair in (
|
( r'@RTR_SIGNAL@', self.RTR if hasattr(self,'RTR') else self.RTRn if hasattr(self,'RTRn') else '', ),
|
( r'@RTR_SIGNAL@', self.RTR if hasattr(self,'RTR') else self.RTRn if hasattr(self,'RTRn') else '', ),
|
( r'@RTR_INVERT@', '' if hasattr(self,'RTR') else '!', ),
|
( r'@RTRN_INVERT@', '!' if hasattr(self,'RTR') else '', ),
|
( r'\bL__', 'L__@NAME@__', ),
|
( r'\bL__', 'L__@NAME@__', ),
|
( r'\bgen__', 'gen__@NAME@__', ),
|
( r'\bgen__', 'gen__@NAME@__', ),
|
( r'\bs__', 's__@NAME@__', ),
|
( r'\bs__', 's__@NAME@__', ),
|
( r'@INPORT@', self.insignal, ),
|
( r'@INPORT@', self.insignal, ),
|
( r'@BAUDMETHOD@', str(self.baudmethod), ),
|
( r'@BAUDMETHOD@', str(self.baudmethod), ),
|
| Line 306... |
Line 324... |
( r'@INFIFO@', str(self.inFIFO), ),
|
( r'@INFIFO@', str(self.inFIFO), ),
|
( r'@ENABLED@', self.CTS if hasattr(self,'CTS') else ('!%s' % self.CTSn) if hasattr(self,'CTSn') else '1\'b1', ),
|
( r'@ENABLED@', self.CTS if hasattr(self,'CTS') else ('!%s' % self.CTSn) if hasattr(self,'CTSn') else '1\'b1', ),
|
( r'@NSTOP@', str(self.nStop), ),
|
( r'@NSTOP@', str(self.nStop), ),
|
( r'@OUTFIFO@', str(self.outFIFO), ),
|
( r'@OUTFIFO@', str(self.outFIFO), ),
|
( r'@NAME@', self.namestring, ),
|
( r'@NAME@', self.namestring, ),
|
|
( r'@RTR_FIFO_COMPARE@', str(CeilLog2(self.rtr_buffer)), ),
|
):
|
):
|
if re.search(subpair[0],body):
|
if re.search(subpair[0],body):
|
body = re.sub(subpair[0],subpair[1],body);
|
body = re.sub(subpair[0],subpair[1],body);
|
body = self.GenVerilogFinal(config,body);
|
body = self.GenVerilogFinal(config,body);
|
fp.write(body);
|
fp.write(body);
|
