| Line 1... |
Line 1... |
################################################################################
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################################################################################
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#
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#
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# Copyright 2013, Sinclair R.F., Inc.
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# Copyright 2013-2014, Sinclair R.F., Inc.
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#
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#
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################################################################################
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################################################################################
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import math;
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import math;
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import re;
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import re;
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| Line 27... |
Line 27... |
[outsignal=o_name] \\
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[outsignal=o_name] \\
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[noSync|sync=n] \\
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[noSync|sync=n] \\
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[noDeglitch|deglitch=n] \\
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[noDeglitch|deglitch=n] \\
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[noInFIFO|inFIFO=n] \\
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[noInFIFO|inFIFO=n] \\
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[noOutFIFO|outFIFO=n] \\
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[noOutFIFO|outFIFO=n] \\
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[{CTS|CTSn}=i_cts_name] \\
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[{RTR|RTRn}=i_rtr_name] \\
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[nStop={1|2}] \n
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[nStop={1|2}] \n
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Where:
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Where:
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inport=I_inport_name
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inport=I_inport_name
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specifies the symbol used by the inport instruction to read a received by
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specifies the symbol used by the inport instruction to read a received by
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from the peripheral
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from the peripheral
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| Line 95... |
Line 97... |
optionally state that the peripheral will not have an output FIFO
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optionally state that the peripheral will not have an output FIFO
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Note: This is the default.
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Note: This is the default.
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outFIFO=n
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outFIFO=n
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optionally add a FIFO of depth n to the output side of the UART
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optionally add a FIFO of depth n to the output side of the UART
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Note: n must be a power of 2.
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Note: n must be a power of 2.
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CTS=i_cts_name or CTSn=i_cts_name
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optionally specify an input handshake signal to control whether or not the
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peripheral transmits data
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Note: If CTS is specified then the transmitter is active when i_cts_name
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is high. If CTSn is specified then the transmitter is active when
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i_cts_name is low.
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Note: The default, i.e., neither CTS nor CTSn is specified, is to always
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enable the transmitter.
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Note: If there is no FIFO and the CTS/CTSn handshake indicates that the
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data flow is disabled, then the busy signal will be high and the
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processor code must not transmit the next byte.
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RTR=i_rtr_name or RTRn=i_rtr_name
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optionally specify an output handshake signal to indicate that the
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peripheral is ready to receive data
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Note: If RTR is specified then the receiver indicates it is ready when
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i_rtr_name is high. If RTRn is specified then the transmitter
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indicates it is ready when i_rtr_name is low.
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Note: The default, i.e., neither CTS nor CTSn is specified, is to always
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enable the receiver.
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Note: If there is no FIFO and the RTR/RTRn handshake indicates that the
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receiver is not ready as soon as it starts receiving data and
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until that data is read from the peripheral.
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nStop=n
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nStop=n
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optionally configure the peripheral for n stop bits
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optionally configure the peripheral for n stop bits
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default: 1 stop bit
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default: 1 stop bit
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Note: n must be 1 or 2
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Note: n must be 1 or 2
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Note: the peripheral does not accept 1.5 stop bits
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Note: the peripheral does not accept 1.5 stop bits\n
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The following ports are provided by this peripheral:
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The following ports are provided by this peripheral:
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I_inport_name
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I_inport_name
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input a recieved byte from the peripheral
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input a recieved byte from the peripheral
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Note: If there is no input FIFO, then this is the last received byte.
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Note: If there is no input FIFO, then this is the last received byte.
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If there is an input FIFO, then this is the next byte in the FIFO.
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If there is an input FIFO, then this is the next byte in the FIFO.
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| Line 132... |
Line 156... |
accept more writes
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accept more writes
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Note: If there is no FIFO this means that the peripheral is still
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Note: If there is no FIFO this means that the peripheral is still
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transmitting the last byte. If there is an output FIFO it means
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transmitting the last byte. If there is an output FIFO it means
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that it is full.\n
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that it is full.\n
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Note: "Busy" is used rather that "ready" to facilitate loops that wait
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Note: "Busy" is used rather that "ready" to facilitate loops that wait
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for a not-busy status to send the next byte. See the examples below.
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for a not-busy status to send the next byte. See the examples below.\n
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WARNING: The peripheral is very simple and does not protect against writing a
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WARNING: The peripheral is very simple and does not protect against writing a
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new value in the middle of a transmition or writing to a full FIFO.
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new value in the middle of a transmition or writing to a full FIFO.
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Adding such logic would be contrary to the design principle of
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Adding such logic would be contrary to the design principle of
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keeping the HDL small and relying on the assembly code to provide
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keeping the HDL small and relying on the assembly code to provide
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the protection.\n
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the protection.\n
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| Line 152... |
Line 176... |
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def __init__(self,peripheralFile,config,param_list,loc):
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def __init__(self,peripheralFile,config,param_list,loc):
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# Use the externally provided file name for the peripheral
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# Use the externally provided file name for the peripheral
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self.peripheralFile = peripheralFile;
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self.peripheralFile = peripheralFile;
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# Get the parameters.
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# Get the parameters.
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for param_tuple in param_list:
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allowables = (
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param = param_tuple[0];
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( 'CTS', r'i_\w+$', None, ),
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param_arg = param_tuple[1];
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( 'CTSn', r'i_\w+$', None, ),
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for param_test in (
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( 'RTR', r'o_\w+$', None, ),
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( 'RTRn', r'o_\w+$', None, ),
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( 'baudmethod', r'\S+$', lambda v : self.RateMethod(config,v), ),
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('deglitch', r'[1-9]\d*$', int, ),
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('deglitch', r'[1-9]\d*$', int, ),
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( 'inFIFO', r'[1-9]\d*$', lambda v : self.IntPow2(v), ),
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('inempty', r'I_\w+$', None, ),
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('inempty', r'I_\w+$', None, ),
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('inport', r'I_\w+$', None, ),
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('inport', r'I_\w+$', None, ),
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('insignal', r'i_\w+$', None, ),
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('insignal', r'i_\w+$', None, ),
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('noDeglitch', None, None, ),
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('noDeglitch', None, None, ),
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('noInFIFO', None, None, ),
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('noInFIFO', None, None, ),
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('noOutFIFO', None, None, ),
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('noOutFIFO', None, None, ),
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('noSync', None, None, ),
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('noSync', None, None, ),
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('nStop', r'[12]$', int, ),
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('nStop', r'[12]$', int, ),
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( 'outFIFO', r'[1-9]\d*$', lambda v : self.IntPow2(v), ),
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('outport', r'O_\w+$', None, ),
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('outport', r'O_\w+$', None, ),
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('outsignal', r'o_\w+$', None, ),
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('outsignal', r'o_\w+$', None, ),
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('outstatus', r'I_\w+$', None, ),
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('outstatus', r'I_\w+$', None, ),
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('sync', r'[1-9]\d*$', int, ),
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('sync', r'[1-9]\d*$', int, ),
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):
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);
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if param == param_test[0]:
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names = [a[0] for a in allowables];
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self.AddAttr(config,param,param_arg,param_test[1],loc,param_test[2]);
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for param_tuple in param_list:
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break;
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param = param_tuple[0];
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else:
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if param not in names:
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if param == 'baudmethod':
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raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
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self.AddRateMethod(config,param,param_arg,loc);
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param_test = allowables[names.index(param)];
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elif param in ('inFIFO','outFIFO',):
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self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
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self.AddAttr(config,param,param_arg,r'[1-9]\d*$',loc,int);
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x = getattr(self,param);
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if not IsPowerOf2(x):
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raise SSBCCException('%s=%d must be a power of 2 at %s' % (param,x,loc,));
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else:
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raise SSBCCException('Unrecognized parameter at %s: %s' % (loc,param,));
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# Ensure the required parameters are provided.
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# Ensure the required parameters are provided.
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for paramname in (
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for paramname in (
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'baudmethod',
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'baudmethod',
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'inempty',
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'inempty',
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'inport',
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'inport',
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| Line 203... |
Line 225... |
):
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):
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if not hasattr(self,optionalpair[0]):
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if not hasattr(self,optionalpair[0]):
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setattr(self,optionalpair[0],optionalpair[1]);
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setattr(self,optionalpair[0],optionalpair[1]);
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# Ensure exclusive pair configurations are set and consistent.
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# Ensure exclusive pair configurations are set and consistent.
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for exclusivepair in (
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for exclusivepair in (
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( 'CTS', 'CTSn', None, None, ),
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( 'RTR', 'RTRn', None, None, ),
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('noSync', 'sync', 'sync', 3, ),
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('noSync', 'sync', 'sync', 3, ),
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('noDeglitch', 'deglitch', 'noDeglitch', True, ),
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('noDeglitch', 'deglitch', 'noDeglitch', True, ),
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('noInFIFO', 'inFIFO', 'noInFIFO', True, ),
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('noInFIFO', 'inFIFO', 'noInFIFO', True, ),
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('noOutFIFO', 'outFIFO', 'noOutFIFO', True, ),
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('noOutFIFO', 'outFIFO', 'noOutFIFO', True, ),
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):
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):
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if hasattr(self,exclusivepair[0]) and hasattr(self,exclusivepair[1]):
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if hasattr(self,exclusivepair[0]) and hasattr(self,exclusivepair[1]):
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raise SSBCCException('Only one of "%s" and "%s" can be specified at %s' % (exclusivepair[0],exclusivepair[1],loc,));
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raise SSBCCException('Only one of "%s" and "%s" can be specified at %s' % (exclusivepair[0],exclusivepair[1],loc,));
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if not hasattr(self,exclusivepair[0]) and not hasattr(self,exclusivepair[1]):
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if not hasattr(self,exclusivepair[0]) and not hasattr(self,exclusivepair[1]) and exclusivepair[2]:
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setattr(self,exclusivepair[2],exclusivepair[3]);
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setattr(self,exclusivepair[2],exclusivepair[3]);
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if hasattr(self,exclusivepair[0]):
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# Convert configurations to alternative format.
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delattr(self,exclusivepair[0]);
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for equivalent in (
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setattr(self,exclusivepair[1],0);
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( 'noDeglitch', 'deglitch', 0, ),
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( 'noInFIFO', 'inFIFO', 0, ),
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( 'noOutFIFO', 'outFIFO', 0, ),
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( 'noSync', 'sync', 0, ),
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):
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if hasattr(self,equivalent[0]):
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delattr(self,equivalent[0]);
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setattr(self,equivalent[1],equivalent[2]);
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# Set the string used to identify signals associated with this peripheral.
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# Set the string used to identify signals associated with this peripheral.
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self.namestring = self.outsignal;
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self.namestring = self.outsignal;
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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config.AddIO(self.insignal,1,'input',loc);
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for ioEntry in (
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config.AddIO(self.outsignal,1,'output',loc);
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( 'insignal', 1, 'input', ),
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( 'outsignal', 1, 'output', ),
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( 'CTS', 1, 'input', ),
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( 'CTSn', 1, 'input', ),
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( 'RTR', 1, 'output', ),
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( 'RTRn', 1, 'output', ),
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):
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if hasattr(self,ioEntry[0]):
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config.AddIO(getattr(self,ioEntry[0]),ioEntry[1],ioEntry[2],loc);
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config.AddSignal('s__%s__Rx' % self.namestring,8,loc);
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config.AddSignal('s__%s__Rx' % self.namestring,8,loc);
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config.AddSignal('s__%s__Rx_empty' % self.namestring,1,loc);
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config.AddSignal('s__%s__Rx_empty' % self.namestring,1,loc);
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config.AddSignal('s__%s__Rx_rd' % self.namestring,1,loc);
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config.AddSignal('s__%s__Rx_rd' % self.namestring,1,loc);
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config.AddSignal('s__%s__Tx' % self.namestring,8,loc);
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config.AddSignal('s__%s__Tx' % self.namestring,8,loc);
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config.AddSignal('s__%s__Tx_busy' % self.namestring,1,loc);
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config.AddSignal('s__%s__Tx_busy' % self.namestring,1,loc);
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| Line 246... |
Line 285... |
config.functions['clog2'] = True;
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config.functions['clog2'] = True;
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def GenVerilog(self,fp,config):
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def GenVerilog(self,fp,config):
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for bodyextension in ('_Rx.v','_Tx.v',):
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for bodyextension in ('_Rx.v','_Tx.v',):
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body = self.LoadCore(self.peripheralFile,bodyextension);
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body = self.LoadCore(self.peripheralFile,bodyextension);
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if hasattr(self,'RTR') or hasattr(self,'RTRn'):
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body = re.sub(r'@RTR_BEGIN@\n','',body);
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body = re.sub(r'@RTR_END@\n','',body);
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else:
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if re.search(r'@RTR_BEGIN@',body):
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body = re.sub(r'@RTR_BEGIN@.*?@RTR_END@\n','',body,flags=re.DOTALL);
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for subpair in (
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for subpair in (
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( r'@RTR_SIGNAL@', self.RTR if hasattr(self,'RTR') else self.RTRn if hasattr(self,'RTRn') else '', ),
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( r'@RTR_INVERT@', '' if hasattr(self,'RTR') else '!', ),
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(r'\bL__', 'L__@NAME@__', ),
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(r'\bL__', 'L__@NAME@__', ),
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(r'\bgen__', 'gen__@NAME@__', ),
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(r'\bgen__', 'gen__@NAME@__', ),
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(r'\bs__', 's__@NAME@__', ),
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(r'\bs__', 's__@NAME@__', ),
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(r'@INPORT@', self.insignal, ),
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(r'@INPORT@', self.insignal, ),
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(r'@BAUDMETHOD@', str(self.baudmethod), ),
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(r'@BAUDMETHOD@', str(self.baudmethod), ),
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(r'@SYNC@', str(self.sync), ),
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(r'@SYNC@', str(self.sync), ),
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(r'@DEGLITCH@', str(self.deglitch), ),
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(r'@DEGLITCH@', str(self.deglitch), ),
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(r'@INFIFO@', str(self.inFIFO), ),
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(r'@INFIFO@', str(self.inFIFO), ),
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( r'@ENABLED@', self.CTS if hasattr(self,'CTS') else ('!%s' % self.CTSn) if hasattr(self,'CTSn') else '1\'b1', ),
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(r'@NSTOP@', str(self.nStop), ),
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(r'@NSTOP@', str(self.nStop), ),
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(r'@OUTFIFO@', str(self.outFIFO), ),
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(r'@OUTFIFO@', str(self.outFIFO), ),
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(r'@NAME@', self.namestring, ),
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(r'@NAME@', self.namestring, ),
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):
|
):
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if re.search(subpair[0],body):
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body = re.sub(subpair[0],subpair[1],body);
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body = re.sub(subpair[0],subpair[1],body);
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body = self.GenVerilogFinal(config,body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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fp.write(body);
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No newline at end of file
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No newline at end of file
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