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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [UART_Rx.py] - Diff between revs 6 and 9

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################################################################################
################################################################################
#
#
# Copyright 2013-2014, Sinclair R.F., Inc.
# Copyright 2013-2015, Sinclair R.F., Inc.
#
#
################################################################################
################################################################################
 
 
import math;
import math;
import re;
import re;
 
 
from ssbccPeripheral import SSBCCperipheral
from ssbccPeripheral import SSBCCperipheral
from ssbccUtil import SSBCCException;
from ssbccUtil import CeilLog2
 
from ssbccUtil import SSBCCException
 
 
class UART_Rx(SSBCCperipheral):
class UART_Rx(SSBCCperipheral):
  """
  """
  Receive UART:
  Receive UART:
    1 start bit
    1 start bit
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                       baudmethod={clk/rate|count} \\
                       baudmethod={clk/rate|count} \\
                       [insignal=i_name]           \\
                       [insignal=i_name]           \\
                       [noSync|sync=n]             \\
                       [noSync|sync=n]             \\
                       [noDeglitch|deglitch=n]     \\
                       [noDeglitch|deglitch=n]     \\
                       [noInFIFO|inFIFO=n]         \\
                       [noInFIFO|inFIFO=n]         \\
                       [{RTR|RTRn}=i_rtr_name]     \\
                       [{RTR|RTRn}=o_rtr_name]     \\
 
                       rtr_buffer=n                \\
                       [nStop={1|2}]               \n
                       [nStop={1|2}]               \n
  Where:
  Where:
    inport=I_inport_name
    inport=I_inport_name
      specifies the symbol used by the inport instruction to read a received by
      specifies the symbol used by the inport instruction to read a received by
      from the peripheral
      from the peripheral
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    baudmethod
    baudmethod
      specifies the method to generate the desired bit rate:
      specifies the method to generate the desired bit rate:
      1st method:  clk/rate
      1st method:  clk/rate
        clk is the frequency of "i_clk" in Hz
        clk is the frequency of "i_clk" in Hz
          a number will be interpreted as the clock frequency in Hz
          a number will be interpreted as the clock frequency in Hz
          a symbol will be interpreted as a parameter
          a symbol will be interpreted as a constant or a parameter
            Note:  this parameter must have been declared with a "PARAMETER"
            Note:  the symbol must be declared with the CONSTANT, LOCALPARARM,
            command
                   or PARAMETER configuration command.
        rate is the desired baud rate
        rate is the desired baud rate
          this is specified as per "clk"
          this is specified as per "clk"
      2nd method:
      2nd method:
        specify the number of "i_clk" clock cycles between bit edges
        specify the number of "i_clk" clock cycles between bit edges
      Note:  clk, rate, and count can be parameters or constants.  For example,
      Note:  clk, rate, and count can be parameters or constants.  For example,
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      optionally state that the peripheral will not have an input FIFO
      optionally state that the peripheral will not have an input FIFO
      Note:  This is the default.
      Note:  This is the default.
    inFIFO=n
    inFIFO=n
      optionally add a FIFO of depth n to the input side of the UART
      optionally add a FIFO of depth n to the input side of the UART
      Note:  n must be a power of 2.
      Note:  n must be a power of 2.
    RTR=i_rtr_name or RTRn=i_rtr_name
    RTR=o_rtr_name or RTRn=o_rtr_name
      optionally specify an output handshake signal to indicate that the
      optionally specify an output handshake signal to indicate that the
      peripheral is ready to receive data
      peripheral is ready to receive data
      Note:  If RTR is specified then the receiver indicates it is ready when
      Note:  If RTR is specified then the receiver indicates it is ready when
             i_rtr_name is high.  If RTRn is specified then the transmitter
             o_rtr_name is high.  If RTRn is specified then the transmitter
             indicates it is ready when i_rtr_name is low.
             indicates it is ready when o_rtr_name is low.
      Note:  The default, i.e., neither CTS nor CTSn is specified, is to always
      Note:  The default, i.e., neither CTS nor CTSn is specified, is to always
             enable the receiver.
             enable the receiver.
      Note:  If there is no FIFO and the RTR/RTRn handshake indicates that the
      Note:  If there is no FIFO and the RTR/RTRn handshake indicates that the
             receiver is not ready as soon as it starts receiving data and
             receiver is not ready as soon as it starts receiving data and
             until that data is read from the peripheral.
             until that data is read from the peripheral.
 
      Default:  1
 
    rtr_buffer=n
 
      optionally specify the number of entries in inFIFO to reserve for data
 
      received after the RTR/RTRn signal indicates to stop data flow.
 
      Note:  n must be a power of 2.
 
      Note:  This requires that inFIFO be specified.
 
      Note:  Some USB UARTs  will transmit several characters after the RTR/RTRn
 
             signal indicates to stop the data flow.
    nStop=n
    nStop=n
      optionally configure the peripheral for n stop bits
      optionally configure the peripheral for n stop bits
      default:  1 stop bit
      default:  1 stop bit
      Note:  n must be 1 or 2
      Note:  n must be 1 or 2
      Note:  the peripheral does not accept 1.5 stop bits
      Note:  the peripheral does not accept 1.5 stop bits
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    allowables = (
    allowables = (
      ( 'RTR',          r'o_\w+$',      None,   ),
      ( 'RTR',          r'o_\w+$',      None,   ),
      ( 'RTRn',         r'o_\w+$',      None,   ),
      ( 'RTRn',         r'o_\w+$',      None,   ),
      ( 'baudmethod',   r'\S+$',        lambda v : self.RateMethod(config,v), ),
      ( 'baudmethod',   r'\S+$',        lambda v : self.RateMethod(config,v), ),
      ( 'deglitch',     r'[1-9]\d*$',   int,    ),
      ( 'deglitch',     r'[1-9]\d*$',   int,    ),
      ( 'inFIFO',       r'[1-9]\d*$',   lambda v : self.IntPow2(v), ),
      ( 'inFIFO',       r'[1-9]\d*$',   lambda v : self.IntPow2Method(config,v), ),
      ( 'inempty',      r'I_\w+$',      None,   ),
      ( 'inempty',      r'I_\w+$',      None,   ),
      ( 'inport',       r'I_\w+$',      None,   ),
      ( 'inport',       r'I_\w+$',      None,   ),
      ( 'insignal',     r'i_\w+$',      None,   ),
      ( 'insignal',     r'i_\w+$',      None,   ),
      ( 'noDeglitch',   None,           None,   ),
      ( 'noDeglitch',   None,           None,   ),
      ( 'noInFIFO',     None,           None,   ),
      ( 'noInFIFO',     None,           None,   ),
      ( 'noSync',       None,           None,   ),
      ( 'noSync',       None,           None,   ),
      ( 'nStop',        r'[12]$',       int,    ),
      ( 'nStop',        r'[12]$',       int,    ),
 
      ( 'rtr_buffer',   r'[1-9]\d*$',   lambda v : self.IntPow2Method(config,v), ),
      ( 'sync',         r'[1-9]\d*$',   int,    ),
      ( 'sync',         r'[1-9]\d*$',   int,    ),
    );
    );
    names = [a[0] for a in allowables];
    names = [a[0] for a in allowables];
    for param_tuple in param_list:
    for param_tuple in param_list:
      param = param_tuple[0];
      param = param_tuple[0];
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        ( 'insignal',   'i_UART_Rx',    ),
        ( 'insignal',   'i_UART_Rx',    ),
        ( 'nStop',      1,              ),
        ( 'nStop',      1,              ),
      ):
      ):
      if not hasattr(self,optionalpair[0]):
      if not hasattr(self,optionalpair[0]):
        setattr(self,optionalpair[0],optionalpair[1]);
        setattr(self,optionalpair[0],optionalpair[1]);
 
    # Ensure the rtr_buffer, if specified, is consistent with the inFIFO
 
    # specification.
 
    if hasattr(self,'rtr_buffer'):
 
      if not hasattr(self,'inFIFO'):
 
        raise SSBCCException('rtr_buffer specification requires simultaneous inFIFO specification at %s' % loc);
 
      if not self.rtr_buffer < self.inFIFO:
 
        raise SSBCCException('rtr_buffer=%d specification must be less than the inFIFO=%d specification at %s' % (self.rtr_buffer,self.inFIFO,loc,));
 
    else:
 
      self.rtr_buffer = 1;
    # Ensure exclusive pair configurations are set and consistent.
    # Ensure exclusive pair configurations are set and consistent.
    for exclusivepair in (
    for exclusivepair in (
        ( 'RTR',        'RTRn',         None,           None,   ),
        ( 'RTR',        'RTRn',         None,           None,   ),
        ( 'noSync',     'sync',         'sync',         3,      ),
        ( 'noSync',     'sync',         'sync',         3,      ),
        ( 'noDeglitch', 'deglitch',     'noDeglitch',   True,   ),
        ( 'noDeglitch', 'deglitch',     'noDeglitch',   True,   ),
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        body = re.sub(r'@RTR_END@\n','',body);
        body = re.sub(r'@RTR_END@\n','',body);
      else:
      else:
        body = re.sub(r'@RTR_BEGIN@.*?@RTR_END@\n','',body,flags=re.DOTALL);
        body = re.sub(r'@RTR_BEGIN@.*?@RTR_END@\n','',body,flags=re.DOTALL);
      for subpair in (
      for subpair in (
          ( r'@RTR_SIGNAL@',    self.RTR if hasattr(self,'RTR') else self.RTRn if hasattr(self,'RTRn') else '', ),
          ( r'@RTR_SIGNAL@',    self.RTR if hasattr(self,'RTR') else self.RTRn if hasattr(self,'RTRn') else '', ),
          ( r'@RTR_INVERT@',    '' if hasattr(self,'RTR') else '!', ),
          ( r'@RTRN_INVERT@',           '!' if hasattr(self,'RTR') else '', ),
          ( r'\bL__',           'L__@NAME@__',          ),
          ( r'\bL__',           'L__@NAME@__',          ),
          ( r'\bgen__',         'gen__@NAME@__',        ),
          ( r'\bgen__',         'gen__@NAME@__',        ),
          ( r'\bs__',           's__@NAME@__',          ),
          ( r'\bs__',           's__@NAME@__',          ),
          ( r'@INPORT@',        self.insignal,          ),
          ( r'@INPORT@',        self.insignal,          ),
          ( r'@BAUDMETHOD@',    str(self.baudmethod),   ),
          ( r'@BAUDMETHOD@',    str(self.baudmethod),   ),
          ( r'@SYNC@',          str(self.sync),         ),
          ( r'@SYNC@',          str(self.sync),         ),
          ( r'@DEGLITCH@',      str(self.deglitch),     ),
          ( r'@DEGLITCH@',      str(self.deglitch),     ),
          ( r'@INFIFO@',        str(self.inFIFO),       ),
          ( r'@INFIFO@',        str(self.inFIFO),       ),
          ( r'@NSTOP@',         str(self.nStop),        ),
          ( r'@NSTOP@',         str(self.nStop),        ),
          ( r'@NAME@',          self.namestring,        ),
          ( r'@NAME@',          self.namestring,        ),
 
          ( r'@RTR_FIFO_COMPARE@',      str(CeilLog2(self.rtr_buffer)), ),
        ):
        ):
        if re.search(subpair[0],body):
        if re.search(subpair[0],body):
          body = re.sub(subpair[0],subpair[1],body);
          body = re.sub(subpair[0],subpair[1],body);
      body = self.GenVerilogFinal(config,body);
      body = self.GenVerilogFinal(config,body);
      fp.write(body);
      fp.write(body);

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