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//
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//
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// PERIPHERAL UART_Rx: @NAME@
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// PERIPHERAL UART_Rx: @NAME@
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// Copyright 2013-2015 Sinclair R.F., Inc.
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//
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//
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// Technique:
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// Technique:
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// - optionally synchronize the incoming signal
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// - optionally synchronize the incoming signal
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// - optionally deglitch the incoming signal
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// - optionally deglitch the incoming signal
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// - identify edges, align with value before the edge
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// - identify edges, align with value before the edge
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// - validate bit sequence and output bit sequence at end of last stop bit
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// - validate bit sequence and output bit sequence at end of last stop bit
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// - optional FIFO
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// - optional FIFO
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//
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//
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localparam L__BAUDMETHOD = ((@BAUDMETHOD@)+1)/2;
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localparam L__BAUDMETHOD = ((@BAUDMETHOD@)+1)/2;
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localparam L__BAUDMETHOD_MINUS = L__BAUDMETHOD - 2;
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localparam L__BAUDMETHOD_MINUS = L__BAUDMETHOD - 2;
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localparam L__BAUDMETHOD_NBITS = $clog2(L__BAUDMETHOD+1);
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localparam L__BAUDMETHOD_NBITS = $clog2(L__BAUDMETHOD_MINUS+1);
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localparam L__SYNC_LENGTH = @SYNC@;
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localparam L__SYNC_LENGTH = @SYNC@;
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localparam L__DEGLITCH_LENGTH = @DEGLITCH@;
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localparam L__DEGLITCH_LENGTH = @DEGLITCH@;
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localparam L__NSTOP = @NSTOP@;
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localparam L__NSTOP = @NSTOP@;
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localparam L__NRX = 1+8+L__NSTOP;
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localparam L__NRX = 1+8+L__NSTOP;
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localparam L__EVENT_COUNT = 2*L__NRX-1;
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localparam L__EVENT_COUNT = 2*L__NRX-1;
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s__Rx_wr <= 1'b0;
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s__Rx_wr <= 1'b0;
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s__Rx_count <= s__Rx_count;
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s__Rx_count <= s__Rx_count;
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end
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end
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// Optional FIFO
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// Optional FIFO
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@RTR_BEGIN@
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@RTR_BEGIN@
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reg s__rtr = 1'b1;
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reg s__rtrn = 1'b1; // Disable reception until the core is out of reset.
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@RTR_END@
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@RTR_END@
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if (L__INFIFO == 0) begin : gen__nofifo
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if (L__INFIFO == 0) begin : gen__nofifo
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst) begin
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if (i_rst) begin
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s__Rx_empty <= 1'b1;
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s__Rx_empty <= 1'b1;
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end
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end
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end
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end
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@RTR_BEGIN@
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@RTR_BEGIN@
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__rtr <= 1'b1;
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s__rtrn <= 1'b1;
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else
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else
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s__rtr <= ~s__Rx_idle;
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s__rtrn <= ~s__Rx_idle;
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@RTR_END@
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@RTR_END@
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end else begin : gen__fifo
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end else begin : gen__fifo
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reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_in;
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reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_in;
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reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_out;
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reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_out;
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wire s__Rx_shift;
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wire s__Rx_shift;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_full <= 1'b0;
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s__Rx_full <= 1'b0;
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else
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else
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s__Rx_full <= (s__Rx_fifo_addr_in == (s__Rx_fifo_addr_out ^ { 1'b1, {(L__INFIFO_NBITS){1'b0}} }));
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s__Rx_full <= (s__Rx_fifo_addr_in == (s__Rx_fifo_addr_out ^ { 1'b1, {(L__INFIFO_NBITS){1'b0}} }));
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reg [7:0] s__Rx_fifo_mem[@INFIFO@-1:0];
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reg [7:0] s__Rx_fifo_mem[L__INFIFO-1:0];
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initial s__Rx_fifo_addr_in = {(L__INFIFO_NBITS+1){1'b0}};
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initial s__Rx_fifo_addr_in = {(L__INFIFO_NBITS+1){1'b0}};
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_fifo_addr_in <= {(L__INFIFO_NBITS+1){1'b0}};
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s__Rx_fifo_addr_in <= {(L__INFIFO_NBITS+1){1'b0}};
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else if (s__Rx_wr && (!s__Rx_full || s__Rx_shift)) begin
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else if (s__Rx_wr && (!s__Rx_full || s__Rx_shift)) begin
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end else begin
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end else begin
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s__Rx_fifo_addr_out <= s__Rx_fifo_addr_out;
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s__Rx_fifo_addr_out <= s__Rx_fifo_addr_out;
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s__Rx <= s__Rx;
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s__Rx <= s__Rx;
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end
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end
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@RTR_BEGIN@
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@RTR_BEGIN@
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// Isn't ready to receive if the FIFO is full or if the FIFO is almost full
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// Isn't ready to receive if the FIFO is full or if the FIFO is almost full.
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// and there is incoming data (i.e., receiver is not idle).
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reg [L__INFIFO_NBITS:0] s__Rx_used = {(L__INFIFO_NBITS+1){1'b0}};
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reg s__Rx_idle_s = 1'b0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_idle_s <= 1'b0;
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s__Rx_used <= {(L__INFIFO_NBITS+1){1'b0}};
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else
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else
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s__Rx_idle_s <= s__Rx_idle;
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s__Rx_used <= s__Rx_fifo_addr_in - s__Rx_fifo_addr_out;
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reg s__Rx_wr_s = 1'b0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_wr_s <= 1'b0;
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s__rtrn <= 1'b1;
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else
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else
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s__Rx_wr_s <= s__Rx_wr;
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s__rtrn <= s__Rx_used[L__INFIFO_NBITS] || &(s__Rx_used[L__INFIFO_NBITS-1:@RTR_FIFO_COMPARE@]);
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reg s__Rx_busy = 1'b0;
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always @ (posedge i_clk)
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if (i_rst)
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s__Rx_busy <= 1'b0;
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else if ({s__Rx_idle_s, s__Rx_idle} == 2'b10)
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s__Rx_busy <= 1'b1;
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else if (s__Rx_wr_s)
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s__Rx_busy <= 1'b0;
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else
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s__Rx_busy <= s__Rx_busy;
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reg s__Rx_almost_full = 1'b0;
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always @ (posedge i_clk)
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if (i_rst)
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s__Rx_almost_full <= 1'b0;
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else
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s__Rx_almost_full <= (s__Rx_fifo_addr_in == (s__Rx_fifo_addr_out + { 1'b0, {(L__INFIFO_NBITS){1'b1}} }));
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always @ (posedge i_clk)
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if (i_rst)
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s__rtr <= 1'b1;
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else
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// s__rtr <= ~(s__Rx_full || (s__Rx_almost_full && ~s__Rx_idle));
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s__rtr <= ~(s__Rx_full || (s__Rx_almost_full && s__Rx_busy));
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@RTR_END@
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@RTR_END@
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end
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end
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@RTR_BEGIN@
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@RTR_BEGIN@
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always @ (*)
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always @ (*)
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@RTR_SIGNAL@ <= @RTR_INVERT@s__rtr;
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@RTR_SIGNAL@ = @RTRN_INVERT@s__rtrn;
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@RTR_END@
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@RTR_END@
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endgenerate
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endgenerate
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No newline at end of file
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No newline at end of file
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