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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [UART_Rx.v] - Diff between revs 6 and 9

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//
//
// PERIPHERAL UART_Rx:  @NAME@
// PERIPHERAL UART_Rx:  @NAME@
 
// Copyright 2013-2015 Sinclair R.F., Inc.
//
//
// Technique:
// Technique:
// - optionally synchronize the incoming signal
// - optionally synchronize the incoming signal
// - optionally deglitch the incoming signal
// - optionally deglitch the incoming signal
// - identify edges, align with value before the edge
// - identify edges, align with value before the edge
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// - validate bit sequence and output bit sequence at end of last stop bit
// - validate bit sequence and output bit sequence at end of last stop bit
// - optional FIFO
// - optional FIFO
//
//
localparam L__BAUDMETHOD = ((@BAUDMETHOD@)+1)/2;
localparam L__BAUDMETHOD = ((@BAUDMETHOD@)+1)/2;
localparam L__BAUDMETHOD_MINUS = L__BAUDMETHOD - 2;
localparam L__BAUDMETHOD_MINUS = L__BAUDMETHOD - 2;
localparam L__BAUDMETHOD_NBITS = $clog2(L__BAUDMETHOD+1);
localparam L__BAUDMETHOD_NBITS = $clog2(L__BAUDMETHOD_MINUS+1);
localparam L__SYNC_LENGTH = @SYNC@;
localparam L__SYNC_LENGTH = @SYNC@;
localparam L__DEGLITCH_LENGTH = @DEGLITCH@;
localparam L__DEGLITCH_LENGTH = @DEGLITCH@;
localparam L__NSTOP = @NSTOP@;
localparam L__NSTOP = @NSTOP@;
localparam L__NRX = 1+8+L__NSTOP;
localparam L__NRX = 1+8+L__NSTOP;
localparam L__EVENT_COUNT = 2*L__NRX-1;
localparam L__EVENT_COUNT = 2*L__NRX-1;
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    s__Rx_wr <= 1'b0;
    s__Rx_wr <= 1'b0;
    s__Rx_count <= s__Rx_count;
    s__Rx_count <= s__Rx_count;
  end
  end
// Optional FIFO
// Optional FIFO
@RTR_BEGIN@
@RTR_BEGIN@
reg s__rtr = 1'b1;
reg s__rtrn = 1'b1; // Disable reception until the core is out of reset.
@RTR_END@
@RTR_END@
if (L__INFIFO == 0) begin : gen__nofifo
if (L__INFIFO == 0) begin : gen__nofifo
  always @ (posedge i_clk)
  always @ (posedge i_clk)
    if (i_rst) begin
    if (i_rst) begin
      s__Rx_empty <= 1'b1;
      s__Rx_empty <= 1'b1;
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      end
      end
    end
    end
  @RTR_BEGIN@
  @RTR_BEGIN@
  always @ (posedge i_clk)
  always @ (posedge i_clk)
    if (i_rst)
    if (i_rst)
      s__rtr <= 1'b1;
      s__rtrn <= 1'b1;
    else
    else
      s__rtr <= ~s__Rx_idle;
      s__rtrn <= ~s__Rx_idle;
  @RTR_END@
  @RTR_END@
end else begin : gen__fifo
end else begin : gen__fifo
  reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_in;
  reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_in;
  reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_out;
  reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_out;
  wire s__Rx_shift;
  wire s__Rx_shift;
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  always @ (posedge i_clk)
  always @ (posedge i_clk)
    if (i_rst)
    if (i_rst)
      s__Rx_full <= 1'b0;
      s__Rx_full <= 1'b0;
    else
    else
      s__Rx_full <= (s__Rx_fifo_addr_in == (s__Rx_fifo_addr_out ^ { 1'b1, {(L__INFIFO_NBITS){1'b0}} }));
      s__Rx_full <= (s__Rx_fifo_addr_in == (s__Rx_fifo_addr_out ^ { 1'b1, {(L__INFIFO_NBITS){1'b0}} }));
  reg [7:0] s__Rx_fifo_mem[@INFIFO@-1:0];
  reg [7:0] s__Rx_fifo_mem[L__INFIFO-1:0];
  initial s__Rx_fifo_addr_in = {(L__INFIFO_NBITS+1){1'b0}};
  initial s__Rx_fifo_addr_in = {(L__INFIFO_NBITS+1){1'b0}};
  always @ (posedge i_clk)
  always @ (posedge i_clk)
    if (i_rst)
    if (i_rst)
      s__Rx_fifo_addr_in <= {(L__INFIFO_NBITS+1){1'b0}};
      s__Rx_fifo_addr_in <= {(L__INFIFO_NBITS+1){1'b0}};
    else if (s__Rx_wr && (!s__Rx_full || s__Rx_shift)) begin
    else if (s__Rx_wr && (!s__Rx_full || s__Rx_shift)) begin
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    end else begin
    end else begin
      s__Rx_fifo_addr_out <= s__Rx_fifo_addr_out;
      s__Rx_fifo_addr_out <= s__Rx_fifo_addr_out;
      s__Rx <= s__Rx;
      s__Rx <= s__Rx;
    end
    end
  @RTR_BEGIN@
  @RTR_BEGIN@
  // Isn't ready to receive if the FIFO is full or if the FIFO is almost full
  // Isn't ready to receive if the FIFO is full or if the FIFO is almost full.
  // and there is incoming data (i.e., receiver is not idle).
  reg [L__INFIFO_NBITS:0] s__Rx_used = {(L__INFIFO_NBITS+1){1'b0}};
  reg s__Rx_idle_s = 1'b0;
 
  always @ (posedge i_clk)
  always @ (posedge i_clk)
    if (i_rst)
    if (i_rst)
      s__Rx_idle_s <= 1'b0;
      s__Rx_used <= {(L__INFIFO_NBITS+1){1'b0}};
    else
    else
      s__Rx_idle_s <= s__Rx_idle;
      s__Rx_used <= s__Rx_fifo_addr_in - s__Rx_fifo_addr_out;
  reg s__Rx_wr_s = 1'b0;
 
  always @ (posedge i_clk)
  always @ (posedge i_clk)
    if (i_rst)
    if (i_rst)
      s__Rx_wr_s <= 1'b0;
      s__rtrn <= 1'b1;
    else
    else
      s__Rx_wr_s <= s__Rx_wr;
      s__rtrn <= s__Rx_used[L__INFIFO_NBITS] || &(s__Rx_used[L__INFIFO_NBITS-1:@RTR_FIFO_COMPARE@]);
  reg s__Rx_busy = 1'b0;
 
  always @ (posedge i_clk)
 
    if (i_rst)
 
      s__Rx_busy <= 1'b0;
 
    else if ({s__Rx_idle_s, s__Rx_idle} == 2'b10)
 
      s__Rx_busy <= 1'b1;
 
    else if (s__Rx_wr_s)
 
      s__Rx_busy <= 1'b0;
 
    else
 
      s__Rx_busy <= s__Rx_busy;
 
  reg s__Rx_almost_full = 1'b0;
 
  always @ (posedge i_clk)
 
    if (i_rst)
 
      s__Rx_almost_full <= 1'b0;
 
    else
 
      s__Rx_almost_full <= (s__Rx_fifo_addr_in == (s__Rx_fifo_addr_out + { 1'b0, {(L__INFIFO_NBITS){1'b1}} }));
 
  always @ (posedge i_clk)
 
    if (i_rst)
 
      s__rtr <= 1'b1;
 
    else
 
//      s__rtr <= ~(s__Rx_full  || (s__Rx_almost_full && ~s__Rx_idle));
 
      s__rtr <= ~(s__Rx_full  || (s__Rx_almost_full && s__Rx_busy));
 
  @RTR_END@
  @RTR_END@
end
end
@RTR_BEGIN@
@RTR_BEGIN@
always @ (*)
always @ (*)
  @RTR_SIGNAL@ <= @RTR_INVERT@s__rtr;
  @RTR_SIGNAL@ = @RTRN_INVERT@s__rtrn;
@RTR_END@
@RTR_END@
endgenerate
endgenerate
 
 
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