URL
https://opencores.org/ocsvn/ssbcc/ssbcc/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 6 |
| Line 6... |
Line 6... |
localparam L__COUNT_NBITS = $clog2(L__COUNT+1);
|
localparam L__COUNT_NBITS = $clog2(L__COUNT+1);
|
localparam L__NTX = 1+8+@NSTOP@-1;
|
localparam L__NTX = 1+8+@NSTOP@-1;
|
localparam L__NTX_NBITS = $clog2((L__NTX==0)?1:L__NTX);
|
localparam L__NTX_NBITS = $clog2((L__NTX==0)?1:L__NTX);
|
generate
|
generate
|
reg [7:0] s__Tx_data;
|
reg [7:0] s__Tx_data;
|
|
wire s__Tx_enabled = @ENABLED@;
|
reg s__Tx_go;
|
reg s__Tx_go;
|
reg s__Tx_uart_busy;
|
reg s__Tx_uart_busy;
|
if (@OUTFIFO@ == 0) begin : gen__nooutfifo
|
if (@OUTFIFO@ == 0) begin : gen__nooutfifo
|
always @ (s__Tx_uart_busy)
|
always @ (s__Tx_uart_busy)
|
s__Tx_busy = s__Tx_uart_busy;
|
s__Tx_busy = s__Tx_uart_busy || !s__Tx_enabled;
|
always @ (s__Tx)
|
always @ (s__Tx)
|
s__Tx_data = s__Tx;
|
s__Tx_data = s__Tx;
|
always @ (s__Tx_wr)
|
always @ (s__Tx_wr)
|
s__Tx_go = s__Tx_wr;
|
s__Tx_go = s__Tx_wr;
|
end else begin : gen__outfifo
|
end else begin : gen__outfifo
|
| Line 41... |
Line 42... |
end
|
end
|
initial s__Tx_go = 1'b0;
|
initial s__Tx_go = 1'b0;
|
always @ (posedge i_clk)
|
always @ (posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
s__Tx_go <= 1'b0;
|
s__Tx_go <= 1'b0;
|
else if (s__Tx_fifo_has_data && !s__Tx_uart_busy && !s__Tx_go)
|
else if (s__Tx_enabled && s__Tx_fifo_has_data && !s__Tx_uart_busy && !s__Tx_go)
|
s__Tx_go <= 1'b1;
|
s__Tx_go <= 1'b1;
|
else
|
else
|
s__Tx_go <= 1'b0;
|
s__Tx_go <= 1'b0;
|
initial s__Tx_fifo_addr_out = {(L__OUTFIFO_NBITS+1){1'b0}};
|
initial s__Tx_fifo_addr_out = {(L__OUTFIFO_NBITS+1){1'b0}};
|
always @ (posedge i_clk)
|
always @ (posedge i_clk)
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.