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https://opencores.org/ocsvn/ssbcc/ssbcc/trunk
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localparam L__COUNT_NBITS = $clog2(L__COUNT+1);
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localparam L__COUNT_NBITS = $clog2(L__COUNT+1);
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localparam L__NTX = 1+8+@NSTOP@-1;
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localparam L__NTX = 1+8+@NSTOP@-1;
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localparam L__NTX_NBITS = $clog2((L__NTX==0)?1:L__NTX);
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localparam L__NTX_NBITS = $clog2((L__NTX==0)?1:L__NTX);
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generate
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generate
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reg [7:0] s__Tx_data;
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reg [7:0] s__Tx_data;
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wire s__Tx_enabled = @ENABLED@;
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reg s__Tx_go;
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reg s__Tx_go;
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reg s__Tx_uart_busy;
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reg s__Tx_uart_busy;
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if (@OUTFIFO@ == 0) begin : gen__nooutfifo
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if (@OUTFIFO@ == 0) begin : gen__nooutfifo
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always @ (s__Tx_uart_busy)
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always @ (s__Tx_uart_busy)
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s__Tx_busy = s__Tx_uart_busy;
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s__Tx_busy = s__Tx_uart_busy || !s__Tx_enabled;
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always @ (s__Tx)
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always @ (s__Tx)
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s__Tx_data = s__Tx;
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s__Tx_data = s__Tx;
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always @ (s__Tx_wr)
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always @ (s__Tx_wr)
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s__Tx_go = s__Tx_wr;
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s__Tx_go = s__Tx_wr;
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end else begin : gen__outfifo
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end else begin : gen__outfifo
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end
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end
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initial s__Tx_go = 1'b0;
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initial s__Tx_go = 1'b0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Tx_go <= 1'b0;
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s__Tx_go <= 1'b0;
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else if (s__Tx_fifo_has_data && !s__Tx_uart_busy && !s__Tx_go)
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else if (s__Tx_enabled && s__Tx_fifo_has_data && !s__Tx_uart_busy && !s__Tx_go)
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s__Tx_go <= 1'b1;
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s__Tx_go <= 1'b1;
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else
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else
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s__Tx_go <= 1'b0;
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s__Tx_go <= 1'b0;
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initial s__Tx_fifo_addr_out = {(L__OUTFIFO_NBITS+1){1'b0}};
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initial s__Tx_fifo_addr_out = {(L__OUTFIFO_NBITS+1){1'b0}};
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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