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//
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//
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// monitor_stack peripheral
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// monitor_stack peripheral
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// Copyright 2013, Sinclair R.F., Inc.
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// Copyright 2013-2015, Sinclair R.F., Inc.
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//
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//
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// Note: The validity of N and T are not monitored for invalid operations. For
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// Note: The validity of N and T are not monitored for invalid operations. For
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// example, if N is not valid and a "swap" is performed, then the data
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// example, if N is not valid and a "swap" is performed, then the data
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// stack is no longer valid and an error is detected. Thus, the validity
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// stack is no longer valid and an error is detected. Thus, the validity
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// of N and T do not need to be monitored for "swap" operations.
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// of N and T do not need to be monitored for "swap" operations.
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//
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//
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initial s__T_valid = 1'b0;
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initial s__T_valid = 1'b0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__T_valid <= 1'b0;
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s__T_valid <= 1'b0;
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else if (s_interrupt || s_interrupted)
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s__T_valid <= s__T_valid;
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else case (s_bus_t)
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else case (s_bus_t)
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C_BUS_T_OPCODE: s__T_valid <= 1'b1;
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C_BUS_T_OPCODE: s__T_valid <= 1'b1;
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C_BUS_T_N: s__T_valid <= s__N_valid;
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C_BUS_T_N: s__T_valid <= s__N_valid;
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C_BUS_T_PRE: case (s_opcode[0+:2])
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C_BUS_T_PRE: case (s_opcode[0+:2])
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2'b00: s__T_valid <= s__T_valid;
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2'b00: s__T_valid <= s__T_valid;
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end
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end
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if (!s__N_valid && (s_Np_stack_ptr[2+:C_DATA_PTR_WIDTH-2] != {(C_DATA_PTR_WIDTH-2){1'b1}})) begin
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if (!s__N_valid && (s_Np_stack_ptr[2+:C_DATA_PTR_WIDTH-2] != {(C_DATA_PTR_WIDTH-2){1'b1}})) begin
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$display("%12d : Malformed next-to-top-of-data-stack validity in @CORENAME@", $time);
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$display("%12d : Malformed next-to-top-of-data-stack validity in @CORENAME@", $time);
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s__data_stack_error <= 1'b1;
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s__data_stack_error <= 1'b1;
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end
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end
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case (s_bus_t)
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if (s_interrupt || s_interrupted)
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; // do nothing
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else case (s_bus_t)
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C_BUS_T_MATH_ROTATE:
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C_BUS_T_MATH_ROTATE:
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if (!s__T_valid && (s_opcode[0+:3] != 3'h0)) begin
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if (!s__T_valid && (s_opcode[0+:3] != 3'h0)) begin
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$display("%12d : Illegal rotate on invalid top of data stack in @CORENAME@", $time);
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$display("%12d : Illegal rotate on invalid top of data stack in @CORENAME@", $time);
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s__data_stack_error <= 1'b1;
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s__data_stack_error <= 1'b1;
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end
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end
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s__data_stack_error <= 1'b1;
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s__data_stack_error <= 1'b1;
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end
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end
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default:
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default:
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;
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;
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endcase
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endcase
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if ((s_opcode == 9'b00_0111_000) && !s__T_valid) begin
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if (s_interrupt || s_interrupted)
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; // do nothing
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else if ((s_opcode == 9'b00_0111_000) && !s__T_valid) begin
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$display("%12d : Outport with invalid top-of-data-stack in @CORENAME@", $time);
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$display("%12d : Outport with invalid top-of-data-stack in @CORENAME@", $time);
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s__data_stack_error <= 1'b1;
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s__data_stack_error <= 1'b1;
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end
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end
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if ((s_opcode == 9'b00_0111_000) && !s__N_valid && !s__outport_pure_strobe) begin
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if ((s_opcode == 9'b00_0111_000) && !s__N_valid && !s__outport_pure_strobe) begin
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$display("%12d : Outport with invalid next-to-top-of-data-stack in @CORENAME@", $time);
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$display("%12d : Outport with invalid next-to-top-of-data-stack in @CORENAME@", $time);
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst) begin
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if (i_rst) begin
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s__R_is_address <= 1'b0;
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s__R_is_address <= 1'b0;
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s__return_is_address <= {(2**C_RETURN_PTR_WIDTH){1'b0}};
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s__return_is_address <= {(2**C_RETURN_PTR_WIDTH){1'b0}};
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end else if (s_return == C_RETURN_INC) begin
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end else if (s_return == C_RETURN_INC) begin
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s__R_is_address <= (s_bus_r == C_BUS_R_PC);
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s__R_is_address <= s_interrupt || (s_bus_r == C_BUS_R_PC);
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s__return_is_address[s_R_stack_ptr_next] <= s__R_is_address;
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s__return_is_address[s_R_stack_ptr_next] <= s__R_is_address;
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end else if (s_return == C_RETURN_DEC) begin
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end else if (s_return == C_RETURN_DEC) begin
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s__R_is_address <= s__return_is_address[s_R_stack_ptr];
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s__R_is_address <= s__return_is_address[s_R_stack_ptr];
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end
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end
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//
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//
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if (!s__R_address_error) begin
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if (!s__R_address_error) begin
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if ((s_bus_pc == C_BUS_PC_RETURN) && !s__R_is_address) begin
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if ((s_bus_pc == C_BUS_PC_RETURN) && !s__R_is_address) begin
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$display("%12d : Non-address by return instruction in @CORENAME@", $time);
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$display("%12d : Non-address by return instruction in @CORENAME@", $time);
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s__R_address_error <= 1'b1;
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s__R_address_error <= 1'b1;
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end
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end
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if (((s_opcode == 9'b00_0001_001) || (s_opcode == 9'b00_1001_001)) && s__R_is_address) begin
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if (s_interrupt || s_interrupted)
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; // do nothing
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else if (((s_opcode == 9'b00_0001_001) || (s_opcode == 9'b00_1001_001)) && s__R_is_address) begin
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$display("%12d : Copied address to data stack in @CORENAME@", $time);
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$display("%12d : Copied address to data stack in @CORENAME@", $time);
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s__R_address_error <= 1'b1;
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s__R_address_error <= 1'b1;
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end
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end
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end
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end
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//
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//
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s__mem_address_limit[1] = @MEM_LIMIT_1@;
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s__mem_address_limit[1] = @MEM_LIMIT_1@;
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s__mem_address_limit[2] = @MEM_LIMIT_2@;
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s__mem_address_limit[2] = @MEM_LIMIT_2@;
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s__mem_address_limit[3] = @MEM_LIMIT_3@;
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s__mem_address_limit[3] = @MEM_LIMIT_3@;
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end
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end
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if ((s_opcode[3+:6] == 6'b000110) && ({ 1'b0, s_T } >= @LAST_INPORT@)) begin
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if (s_interrupt || s_interrupted) begin
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// do nothing
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end else if ((s_opcode[3+:6] == 6'b000110) && ({ 1'b0, s_T } >= @LAST_INPORT@)) begin
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$display("%12d : Range error on inport in @CORENAME@", $time);
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$display("%12d : Range error on inport in @CORENAME@", $time);
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s__range_error <= 1'b1;
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s__range_error <= 1'b1;
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end else if ((s_opcode[3+:6] == 6'b000111) && ({ 1'b0, s_T } >= @LAST_OUTPORT@)) begin
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end else if ((s_opcode[3+:6] == 6'b000111) && ({ 1'b0, s_T } >= @LAST_OUTPORT@)) begin
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$display("%12d : Range error on outport in @CORENAME@", $time);
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$display("%12d : Range error on outport in @CORENAME@", $time);
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s__range_error <= 1'b1;
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s__range_error <= 1'b1;
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end
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end
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//
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//
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reg [L__TRACE_SIZE-1:0] s__history[@HISTORY@-1:0];
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reg [L__TRACE_SIZE-1:0] s__history[@HISTORY@-1:0];
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reg [8:0] s__opcode_s = 9'b0;
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reg [8:0] s__opcode_s = 9'b0;
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reg [C_PC_WIDTH-1:0] s__PC_s[1:0];
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reg [C_PC_WIDTH-1:0] s__PC_s[1:0];
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reg s__interrupt_s = 1'b0;
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reg s__interrupted_s = 1'b0;
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integer ix__history;
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integer ix__history;
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initial begin
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initial begin
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for (ix__history=0; ix__history<@HISTORY@; ix__history=ix__history+1)
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for (ix__history=0; ix__history<@HISTORY@; ix__history=ix__history+1)
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s__history[ix__history] = {(L__TRACE_SIZE){1'b0}};
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s__history[ix__history] = {(L__TRACE_SIZE){1'b0}};
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s__PC_s[0] = {(C_PC_WIDTH){1'b0}};
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s__PC_s[0] = {(C_PC_WIDTH){1'b0}};
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s__PC_s[1] = {(C_PC_WIDTH){1'b0}};
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s__PC_s[1] = {(C_PC_WIDTH){1'b0}};
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end
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end
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always @ (posedge i_clk) begin
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always @ (posedge i_clk) begin
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s__PC_s[1] <= s__PC_s[0];
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s__PC_s[1] <= s__PC_s[0];
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s__PC_s[0] <= s_PC;
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s__PC_s[0] <= s_PC;
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s__interrupt_s <= s_interrupt;
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s__interrupted_s <= s_interrupted;
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s__opcode_s <= s_opcode;
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s__opcode_s <= s_opcode;
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for (ix__history=1; ix__history<@HISTORY@; ix__history=ix__history+1)
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for (ix__history=1; ix__history<@HISTORY@; ix__history=ix__history+1)
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s__history[ix__history-1] <= s__history[ix__history];
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s__history[ix__history-1] <= s__history[ix__history];
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s__history[@HISTORY@-1] <= { s__PC_s[1], s__opcode_s, s_Np_stack_ptr, s__N_valid, s_N, s__T_valid, s_T, s__R_valid, s_R, s_R_stack_ptr };
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s__history[@HISTORY@-1] <= { s__interrupt_s, s__interrupted_s, s__PC_s[1], s__opcode_s, s_Np_stack_ptr, s__N_valid, s_N, s__T_valid, s_T, s__R_valid, s_R, s_R_stack_ptr };
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end
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end
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wire s_terminate = s__PC_error || s__data_stack_error || s__return_stack_error || s__R_address_error || s__range_error;
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wire s_terminate = s__PC_error || s__data_stack_error || s__return_stack_error || s__R_address_error || s__range_error;
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always @ (posedge s_terminate) begin
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always @ (posedge s_terminate) begin
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for (ix__history=0; ix__history<@HISTORY@; ix__history=ix__history+1)
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for (ix__history=0; ix__history<@HISTORY@; ix__history=ix__history+1)
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display_trace(s__history[ix__history]);
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display_trace(s__history[ix__history]);
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display_trace({ s__PC_s[1], s__opcode_s, s_Np_stack_ptr, s__N_valid, s_N, s__T_valid, s_T, s__R_valid, s_R, s_R_stack_ptr });
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display_trace({ s_interrupt, s_interrupted, s__PC_s[1], s__opcode_s, s_Np_stack_ptr, s__N_valid, s_N, s__T_valid, s_T, s__R_valid, s_R, s_R_stack_ptr });
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$finish;
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$finish;
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end
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end
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endgenerate
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endgenerate
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No newline at end of file
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No newline at end of file
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