| Line 20... |
Line 20... |
data=<o_data> \\
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data=<o_data> \\
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data_rd=<i_data_rd> \\
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data_rd=<i_data_rd> \\
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data_empty=<o_data_empty> \\
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data_empty=<o_data_empty> \\
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outport=<O_data> \\
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outport=<O_data> \\
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infull=<I_full> \\
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infull=<I_full> \\
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depth=<N> \n
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depth=<N> \\
|
|
[outempty=I_empty] \n
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Where:
|
Where:
|
outclk=<i_clock>
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outclk=<i_clock>
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specifies the name of the asynchronous read clock
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specifies the name of the asynchronous read clock
|
data=<o_data>
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data=<o_data>
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specifies the name of the 8-bit outgoing data
|
specifies the name of the 8-bit outgoing data
|
| Line 37... |
Line 38... |
infull=<I_full>
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infull=<I_full>
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specifies the symbol used by the inport instruction to read the "full"
|
specifies the symbol used by the inport instruction to read the "full"
|
status of the FIFO
|
status of the FIFO
|
depth=<N>
|
depth=<N>
|
specifies the depth of the FIFO
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specifies the depth of the FIFO
|
Note: N must be a power of 2 and must be at least 16.\n
|
Note: N must be a power of 2 and must be at least 16.
|
|
outempty=O_empty
|
|
optionally specifies the name of an input port for the processor to access
|
|
the "empty" status of the FIFO\n
|
Example: Provide a FIFO to an external device or IP.\n
|
Example: Provide a FIFO to an external device or IP.\n
|
The PERIPHERAL statement would be:\n
|
The PERIPHERAL statement would be:\n
|
PERIPHERAL outFIFO_async outclk=i_dev_clk \\
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PERIPHERAL outFIFO_async outclk=i_dev_clk \\
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data=o_dev_data \\
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data=o_dev_data \\
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data_rd=i_dev_data_rd \\
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data_rd=i_dev_data_rd \\
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| Line 52... |
Line 56... |
To put a text message in the FIFO, similarly to a UART, do the following:\n
|
To put a text message in the FIFO, similarly to a UART, do the following:\n
|
N"message"
|
N"message"
|
:loop
|
:loop
|
.inport(I_DATA_FIFO_FULL) .jumpc(loop)
|
.inport(I_DATA_FIFO_FULL) .jumpc(loop)
|
.outport(O_DATA_FIFO)
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.outport(O_DATA_FIFO)
|
.jumpc(loop,nop)
|
.jumpc(loop,nop)\n
|
|
Interrupt handler: "!s__<data>__outempty_in" is is suitable input to an
|
|
interrupt handler where "<data>" is the name assigned to "data". This signal
|
|
is high when the FIFO is empty, so a falling edge (the leading "!") is a
|
|
suitable condition for the interrupt to occur.
|
"""
|
"""
|
|
|
def __init__(self,peripheralFile,config,param_list,loc):
|
def __init__(self,peripheralFile,config,param_list,loc):
|
# Use the externally provided file name for the peripheral
|
# Use the externally provided file name for the peripheral
|
self.peripheralFile = peripheralFile;
|
self.peripheralFile = peripheralFile;
|
| Line 67... |
Line 75... |
('data_rd', r'i_\w+$', None, ),
|
('data_rd', r'i_\w+$', None, ),
|
('data_empty', r'o_\w+$', None, ),
|
('data_empty', r'o_\w+$', None, ),
|
('outport', r'O_\w+$', None, ),
|
('outport', r'O_\w+$', None, ),
|
('infull', r'I_\w+$', None, ),
|
('infull', r'I_\w+$', None, ),
|
('depth', r'[1-9]\d*$', lambda v : self.IntPow2Method(config,v,lowLimit=16), ),
|
('depth', r'[1-9]\d*$', lambda v : self.IntPow2Method(config,v,lowLimit=16), ),
|
|
('outempty', r'I_\w+$', None, ),
|
);
|
);
|
names = [a[0] for a in allowables];
|
names = [a[0] for a in allowables];
|
for param_tuple in param_list:
|
for param_tuple in param_list:
|
param = param_tuple[0];
|
param = param_tuple[0];
|
if param not in names:
|
if param not in names:
|
raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
|
raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
|
param_test = allowables[names.index(param)];
|
param_test = allowables[names.index(param)];
|
self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
|
self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
|
# Ensure the required parameters are provided.
|
# Ensure the required parameters are provided.
|
for paramname in names:
|
for paramname in names:
|
|
if paramname in ('outempty',):
|
|
continue;
|
if not hasattr(self,paramname):
|
if not hasattr(self,paramname):
|
raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
|
raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
|
# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
|
# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
|
config.AddIO(self.outclk,1,'input',loc);
|
config.AddIO(self.outclk,1,'input',loc);
|
config.AddIO(self.data,8,'output',loc);
|
config.AddIO(self.data,8,'output',loc);
|
| Line 93... |
Line 104... |
),loc);
|
),loc);
|
config.AddInport((self.infull,
|
config.AddInport((self.infull,
|
('s__%s__full' % self.data,1,'data',),
|
('s__%s__full' % self.data,1,'data',),
|
),loc);
|
),loc);
|
|
|
|
if hasattr(self,'outempty'):
|
|
self.outempty_name = 's__%s__outempty_in' % self.data;
|
|
config.AddSignalWithInit(self.outempty_name,1,'1\'b1',loc);
|
|
self.ix_outempty = config.NInports();
|
|
config.AddInport((self.outempty,
|
|
(self.outempty_name,1,'data',),
|
|
),loc);
|
|
|
def GenVerilog(self,fp,config):
|
def GenVerilog(self,fp,config):
|
body = self.LoadCore(self.peripheralFile,'.v');
|
body = self.LoadCore(self.peripheralFile,'.v');
|
|
if hasattr(self,'outempty'):
|
|
body_outempty = """\
|
|
always @ (posedge i_clk)
|
|
s__outempty_in <= (s__delta_clk == @DEPTH_NBITS@'d0);
|
|
"""
|
|
else:
|
|
body_outempty = '';
|
for subpair in (
|
for subpair in (
|
|
( r'@OUTEMPTY@\n', body_outempty, ),
|
( r'@DATA@', self.data, ),
|
( r'@DATA@', self.data, ),
|
( r'@DATA_EMPTY@', self.data_empty, ),
|
( r'@DATA_EMPTY@', self.data_empty, ),
|
( r'@DATA_RD@', self.data_rd, ),
|
( r'@DATA_RD@', self.data_rd, ),
|
( r'@DEPTH@', str(self.depth), ),
|
( r'@DEPTH@', str(self.depth), ),
|
( r'@DEPTH-1@', str(self.depth-1), ),
|
( r'@DEPTH-1@', str(self.depth-1), ),
|
