| Line 17... |
Line 17... |
DRV8825. It includes a buffer which can be used to store acceleration,
|
DRV8825. It includes a buffer which can be used to store acceleration,
|
motion, and deceleration profiles and returns a "completed" status to the
|
motion, and deceleration profiles and returns a "completed" status to the
|
micro controller.\n
|
micro controller.\n
|
The core runs accumulators for the angle and the rate. I.e. the rate is an
|
The core runs accumulators for the angle and the rate. I.e. the rate is an
|
accumulated sum of the initial rate and the commanded acceleration and the
|
accumulated sum of the initial rate and the commanded acceleration and the
|
angle is an accumulation of this possibly changing rate. The direction signal
|
angle is an accumulation of this possibly changing rate. The direction
|
to the stepper motor is the sign bit from the accumulated rate. The "step"
|
signal (if present) to the stepper motor is the sign bit from the accumulated
|
signal to the stepper motor driver is strobed every time the accumulated angle
|
rate. The "step" signal to the stepper motor driver is strobed every time
|
overflows or underflows and the direction bit to the driver is set according
|
the accumulated angle overflows or underflows and the direction bit to the
|
to whether the accumulated angle overflowed or underflowed.\n
|
driver is set according to whether the accumulated angle overflowed or
|
|
underflowed.\n
|
The motor control word consists of the following signals:
|
The motor control word consists of the following signals:
|
initial rate
|
initial rate
|
acceleration
|
acceleration
|
number of steps to be performed this control word
|
number of steps to be performed this control word
|
optional mode specification
|
optional mode specification
|
| Line 41... |
Line 42... |
PERIPHERAL stepper_motor basename=name \\
|
PERIPHERAL stepper_motor basename=name \\
|
outcontrol=O_name \\
|
outcontrol=O_name \\
|
outrecord=O_name \\
|
outrecord=O_name \\
|
outrun=O_name \\
|
outrun=O_name \\
|
indone=I_name \\
|
indone=I_name \\
|
inerror=I_name \\
|
[inerror=I_name] \\
|
|
[nodir] \\
|
ratemethod={CLK_FREQ_HZ/RATE_HZ|count} \\
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ratemethod={CLK_FREQ_HZ/RATE_HZ|count} \\
|
ratescale=N_rate_scale \\
|
ratescale=N_rate_scale \\
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rateres=N_rate \\
|
rateres=N_rate \\
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accelscale=N_accel_scale \\
|
accelscale=N_accel_scale \\
|
accelres=N_accel \\
|
accelres=N_accel \\
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| Line 57... |
Line 59... |
PERIPHERAL stepper_motor basename=name \\
|
PERIPHERAL stepper_motor basename=name \\
|
master=mastername \\
|
master=mastername \\
|
outrecord=O_name \\
|
outrecord=O_name \\
|
outrun=O_name \\
|
outrun=O_name \\
|
indone=I_name \\
|
indone=I_name \\
|
inerror=I_name \\
|
[nodir] \\
|
|
[inerror=I_name] \\
|
[FIFO=N_fifo]\n
|
[FIFO=N_fifo]\n
|
Where:
|
Where:
|
basename=name
|
basename=name
|
specifies the name used to contruct the I/O signals
|
specifies the name used to contruct the I/O signals
|
Note: The name must start with an alphabetic character.
|
Note: The name must start with an alphabetic character.
|
| Line 90... |
Line 93... |
indone=I_name
|
indone=I_name
|
specifies the port used to determine whether or not the operations in the
|
specifies the port used to determine whether or not the operations in the
|
FIFO have finished
|
FIFO have finished
|
Note: The name must start with "I_".
|
Note: The name must start with "I_".
|
inerror=I_name
|
inerror=I_name
|
specifies the port used to read the error status from the stepper motor
|
optionally specifies the port used to read the error status from the
|
controller
|
stepper motor controller
|
Note: The name must start with "I_".
|
Note: The name must start with "I_".
|
|
nodir
|
|
optionally specify that the stepper motor does not generate a direction
|
|
bit
|
ratemethod
|
ratemethod
|
specified the method to generate the internal clock rate from the
|
specified the method to generate the internal clock rate from the
|
processor clock
|
processor clock
|
1st method: CLK_FREQ_HZ/RATE_HZ
|
1st method: CLK_FREQ_HZ/RATE_HZ
|
CLK_FREQ_HZ is the frequency of "i_clk" in Hz
|
CLK_FREQ_HZ is the frequency of "i_clk" in Hz
|
| Line 314... |
Line 320... |
( 'countwidth', r'\S+$', lambda v : self.IntMethod(config,v,lowLimit=1), ),
|
( 'countwidth', r'\S+$', lambda v : self.IntMethod(config,v,lowLimit=1), ),
|
( 'indone', r'I_\w+$', None, ),
|
( 'indone', r'I_\w+$', None, ),
|
( 'inerror', r'I_\w+$', None, ),
|
( 'inerror', r'I_\w+$', None, ),
|
( 'master', r'[A-Za-z]\w*$', None, ),
|
( 'master', r'[A-Za-z]\w*$', None, ),
|
( 'modewidth', r'\S+$', lambda v : self.IntMethod(config,v,lowLimit=1), ),
|
( 'modewidth', r'\S+$', lambda v : self.IntMethod(config,v,lowLimit=1), ),
|
|
( 'nodir', None, None, ),
|
( 'outcontrol', r'O_\w+$', None, ),
|
( 'outcontrol', r'O_\w+$', None, ),
|
( 'outrecord', r'O_\w+$', None, ),
|
( 'outrecord', r'O_\w+$', None, ),
|
( 'outrun', r'O_\w+$', None, ),
|
( 'outrun', r'O_\w+$', None, ),
|
( 'ratemethod', r'\S+$', lambda v : self.RateMethod(config,v), ),
|
( 'ratemethod', r'\S+$', lambda v : self.RateMethod(config,v), ),
|
( 'rateres', r'\S+$', lambda v : self.IntMethod(config,v,lowLimit=1), ),
|
( 'rateres', r'\S+$', lambda v : self.IntMethod(config,v,lowLimit=1), ),
|
| Line 344... |
Line 351... |
)
|
)
|
# Ensure the required parameters are provided.
|
# Ensure the required parameters are provided.
|
reqdParms = (
|
reqdParms = (
|
'basename',
|
'basename',
|
'indone',
|
'indone',
|
'inerror',
|
|
'outrecord',
|
'outrecord',
|
'outrun',
|
'outrun',
|
)
|
)
|
if not hasattr(self,'master'):
|
if not hasattr(self,'master'):
|
reqdParms += tuple([me for me in masterExclude if me not in ('accumres','modewidth',)])
|
reqdParms += tuple([me for me in masterExclude if me not in ('accumres','modewidth',)])
|
| Line 385... |
Line 391... |
if not (self.rateres < self.accelres):
|
if not (self.rateres < self.accelres):
|
raise SSBCCException('rateres should be smaller than accelres at %s' % loc)
|
raise SSBCCException('rateres should be smaller than accelres at %s' % loc)
|
if not (self.rateres <= self.accumres <= self.accelres):
|
if not (self.rateres <= self.accumres <= self.accelres):
|
raise SSBCCException('accumres must be between rateres and accelres at %s' % loc)
|
raise SSBCCException('accumres must be between rateres and accelres at %s' % loc)
|
# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
|
# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
|
|
if not hasattr(self,'nodir'):
|
config.AddIO('o_%s_dir' % self.basename, 1, 'output', loc)
|
config.AddIO('o_%s_dir' % self.basename, 1, 'output', loc)
|
config.AddIO('o_%s_step' % self.basename, 1, 'output', loc)
|
config.AddIO('o_%s_step' % self.basename, 1, 'output', loc)
|
if self.modewidth > 0:
|
if self.modewidth > 0:
|
config.AddIO('o_%s_mode' % self.basename, 1, 'output', loc)
|
config.AddIO('o_%s_mode' % self.basename, 1, 'output', loc)
|
|
if hasattr(self,'inerror'):
|
config.AddIO('i_%s_error' % self.basename, 1, 'input', loc)
|
config.AddIO('i_%s_error' % self.basename, 1, 'input', loc)
|
config.AddSignal('s__%s__done' % self.basename, 1, loc)
|
config.AddSignal('s__%s__done' % self.basename, 1, loc)
|
self.ix_outcontrol = config.NOutports()
|
self.ix_outcontrol = config.NOutports()
|
if not hasattr(self,'master'):
|
if not hasattr(self,'master'):
|
config.AddOutport((self.outcontrol,
|
config.AddOutport((self.outcontrol,
|
| Line 407... |
Line 415... |
self.ix_outrun = config.NOutports()
|
self.ix_outrun = config.NOutports()
|
config.AddOutport((self.outrun,
|
config.AddOutport((self.outrun,
|
True,
|
True,
|
# empty list
|
# empty list
|
),loc)
|
),loc)
|
|
if hasattr(self,'inerror'):
|
config.AddInport((self.inerror,
|
config.AddInport((self.inerror,
|
('i_%s_error' % self.basename, 1, 'data', ),
|
('i_%s_error' % self.basename, 1, 'data', ),
|
), loc)
|
), loc)
|
config.AddInport((self.indone,
|
config.AddInport((self.indone,
|
('s__%s__done' % self.basename, 1, 'data', ),
|
('s__%s__done' % self.basename, 1, 'data', ),
|
| Line 440... |
Line 449... |
if self.modewidth == 0:
|
if self.modewidth == 0:
|
body = re.sub(r'@OUTMODE_BEGIN@.*?@OUTMODE_END@\n','',body,flags=re.DOTALL)
|
body = re.sub(r'@OUTMODE_BEGIN@.*?@OUTMODE_END@\n','',body,flags=re.DOTALL)
|
else:
|
else:
|
body = re.sub(r'@OUTMODE_BEGIN@\n','',body)
|
body = re.sub(r'@OUTMODE_BEGIN@\n','',body)
|
body = re.sub(r'@OUTMODE_END@\n','',body)
|
body = re.sub(r'@OUTMODE_END@\n','',body)
|
|
if hasattr(self,'nodir'):
|
|
body = re.sub(r' *o__dir.*?\n','',body)
|
masterBasename = self.basename if not hasattr(self,'master') else self.master.basename
|
masterBasename = self.basename if not hasattr(self,'master') else self.master.basename
|
for subpair in (
|
for subpair in (
|
( r'@ACCEL_WIDTH@', str(self.accelwidth), ),
|
( r'@ACCEL_WIDTH@', str(self.accelwidth), ),
|
( r'@ACCEL_RES@', str(self.accelres), ),
|
( r'@ACCEL_RES@', str(self.accelres), ),
|
( r'@ACCEL_SCALE@', str(self.accelscale), ),
|
( r'@ACCEL_SCALE@', str(self.accelscale), ),
|
