| Line 54... |
Line 54... |
[modewidth=N_mode] \\
|
[modewidth=N_mode] \\
|
[FIFO=N_fifo]\n
|
[FIFO=N_fifo]\n
|
Or:\n
|
Or:\n
|
PERIPHERAL stepper_motor basename=name \\
|
PERIPHERAL stepper_motor basename=name \\
|
master=mastername \\
|
master=mastername \\
|
outcontrol=O_name \\
|
|
outrecord=O_name \\
|
outrecord=O_name \\
|
outrun=O_name \\
|
outrun=O_name \\
|
indone=I_name \\
|
indone=I_name \\
|
inerror=I_name \\
|
inerror=I_name \\
|
[FIFO=N_fifo]\n
|
[FIFO=N_fifo]\n
|
| Line 72... |
Line 71... |
"i_stepper_error" for the input error signal.
|
"i_stepper_error" for the input error signal.
|
master=mastername
|
master=mastername
|
specifies a preceding stepper_motor peripheral to use for the internal
|
specifies a preceding stepper_motor peripheral to use for the internal
|
clock and to use for the accleration, rate, angle accumulator, and mode
|
clock and to use for the accleration, rate, angle accumulator, and mode
|
sizes
|
sizes
|
|
Note: The "outcontrol" port from the master peripheral is used to queue
|
|
the control words for its slaves.
|
outcontrol=O_name
|
outcontrol=O_name
|
specifies the port used to assemble 8-bit control values into the stepper
|
specifies the port used to assemble 8-bit control values into the stepper
|
motor control word
|
motor control word
|
Note: The name must start with "O_".
|
Note: The name must start with "O_".
|
outrecord=O_name
|
outrecord=O_name
|
| Line 288... |
Line 289... |
Example:
|
Example:
|
Slave a second stepper motor controller peripheral to the preceding
|
Slave a second stepper motor controller peripheral to the preceding
|
periperal.\n
|
periperal.\n
|
PERIPHERAL stepper_motor basename=slave \\
|
PERIPHERAL stepper_motor basename=slave \\
|
master=stepper \\
|
master=stepper \\
|
outcontrol=O_slave_control \\
|
|
outrecord=O_slave_wr \\
|
outrecord=O_slave_wr \\
|
outrun=O_slave_go \\
|
outrun=O_slave_go \\
|
indone=I_slave_done \\
|
indone=I_slave_done \\
|
inerror=I_slave_error\n
|
inerror=I_slave_error\n
|
This controller will use the internal clock generated by the first
|
This controller will use the internal clock generated by the first
|
| Line 335... |
Line 335... |
'accelres',
|
'accelres',
|
'accelscale',
|
'accelscale',
|
'accumres',
|
'accumres',
|
'countwidth',
|
'countwidth',
|
'modewidth',
|
'modewidth',
|
|
'outcontrol',
|
'ratemethod',
|
'ratemethod',
|
'rateres',
|
'rateres',
|
'ratescale',
|
'ratescale',
|
)
|
)
|
# Ensure the required parameters are provided.
|
# Ensure the required parameters are provided.
|
reqdParms = (
|
reqdParms = (
|
'basename',
|
'basename',
|
'indone',
|
'indone',
|
'inerror',
|
'inerror',
|
'outcontrol',
|
|
'outrecord',
|
'outrecord',
|
'outrun',
|
'outrun',
|
)
|
)
|
if not hasattr(self,'master'):
|
if not hasattr(self,'master'):
|
reqdParms += tuple([me for me in masterExclude if me not in ('accumres','modewidth',)])
|
reqdParms += tuple([me for me in masterExclude if me not in ('accumres','modewidth',)])
|
| Line 392... |
Line 392... |
if self.modewidth > 0:
|
if self.modewidth > 0:
|
config.AddIO('o_%s_mode' % self.basename, 1, 'output', loc)
|
config.AddIO('o_%s_mode' % self.basename, 1, 'output', loc)
|
config.AddIO('i_%s_error' % self.basename, 1, 'input', loc)
|
config.AddIO('i_%s_error' % self.basename, 1, 'input', loc)
|
config.AddSignal('s__%s__done' % self.basename, 1, loc)
|
config.AddSignal('s__%s__done' % self.basename, 1, loc)
|
self.ix_outcontrol = config.NOutports()
|
self.ix_outcontrol = config.NOutports()
|
|
if not hasattr(self,'master'):
|
config.AddOutport((self.outcontrol,
|
config.AddOutport((self.outcontrol,
|
False,
|
False,
|
# empty list
|
# empty list
|
),loc)
|
),loc)
|
self.ix_outrecord = config.NOutports()
|
self.ix_outrecord = config.NOutports()
|
| Line 439... |
Line 440... |
if self.modewidth == 0:
|
if self.modewidth == 0:
|
body = re.sub(r'@OUTMODE_BEGIN@.*?@OUTMODE_END@\n','',body,flags=re.DOTALL)
|
body = re.sub(r'@OUTMODE_BEGIN@.*?@OUTMODE_END@\n','',body,flags=re.DOTALL)
|
else:
|
else:
|
body = re.sub(r'@OUTMODE_BEGIN@\n','',body)
|
body = re.sub(r'@OUTMODE_BEGIN@\n','',body)
|
body = re.sub(r'@OUTMODE_END@\n','',body)
|
body = re.sub(r'@OUTMODE_END@\n','',body)
|
|
masterBasename = self.basename if not hasattr(self,'master') else self.master.basename
|
for subpair in (
|
for subpair in (
|
( r'@ACCEL_WIDTH@', str(self.accelwidth), ),
|
( r'@ACCEL_WIDTH@', str(self.accelwidth), ),
|
( r'@ACCEL_RES@', str(self.accelres), ),
|
( r'@ACCEL_RES@', str(self.accelres), ),
|
( r'@ACCEL_SCALE@', str(self.accelscale), ),
|
( r'@ACCEL_SCALE@', str(self.accelscale), ),
|
( r'@ACCUM_RES@', str(self.accumres), ),
|
( r'@ACCUM_RES@', str(self.accumres), ),
|
| Line 467... |
Line 469... |
( r'@RATE_WIDTH@', str(self.ratewidth), ),
|
( r'@RATE_WIDTH@', str(self.ratewidth), ),
|
( r'\bL__', 'L__%s__' % self.basename, ),
|
( r'\bL__', 'L__%s__' % self.basename, ),
|
( r'\bi__', 'i_%s_' % self.basename, ),
|
( r'\bi__', 'i_%s_' % self.basename, ),
|
( r'\bo__', 'o_%s_' % self.basename, ),
|
( r'\bo__', 'o_%s_' % self.basename, ),
|
( r'\bs__', 's__%s__' % self.basename, ),
|
( r'\bs__', 's__%s__' % self.basename, ),
|
( r'@S__CLK_EN@', 's__%s__clk_en' % (self.basename if not hasattr(self,'master') else self.master.basename), ),
|
( r'@S__CLK_EN@', 's__%s__clk_en' % masterBasename, ),
|
|
( r'@S__INPUT_CONTROL_WORD_PACKED@', 's__%s__input_control_word_packed' % masterBasename, ),
|
):
|
):
|
body = re.sub(subpair[0],subpair[1],body)
|
body = re.sub(subpair[0],subpair[1],body)
|
body = self.GenVerilogFinal(config,body)
|
body = self.GenVerilogFinal(config,body)
|
fp.write(body)
|
fp.write(body)
|
|
|
No newline at end of file
|
No newline at end of file
|
