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Line 169... |
tb_AXI4_Lite_Slave_DualPortRAM uut(
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tb_AXI4_Lite_Slave_DualPortRAM uut(
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// synchronous reset and processor clock
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// synchronous reset and processor clock
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.i_rst (s_rst),
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.i_rst (s_rst),
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.i_clk (s_clk),
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.i_clk (s_clk),
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// AXI4-Lite Slave I/F
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// AXI4-Lite Slave I/F
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.i_axi_lite_aresetn (1'b1),
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.axi_lite_aresetn (1'b1),
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.i_axi_lite_aclk (s_aclk),
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.axi_lite_aclk (s_aclk),
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.i_axi_lite_awvalid (s_awvalid),
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.axi_lite_awvalid (s_awvalid),
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.o_axi_lite_awready (s_awready),
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.axi_lite_awready (s_awready),
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.i_axi_lite_awaddr (s_wr_addr),
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.axi_lite_awaddr (s_wr_addr),
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.i_axi_lite_wvalid (s_wvalid),
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.axi_lite_wvalid (s_wvalid),
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.o_axi_lite_wready (s_wready),
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.axi_lite_wready (s_wready),
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.i_axi_lite_wdata (s_wr_data),
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.axi_lite_wdata (s_wr_data),
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.i_axi_lite_wstrb (s_wr_vld),
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.axi_lite_wstrb (s_wr_vld),
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.o_axi_lite_bresp (s_bresp),
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.axi_lite_bresp (s_bresp),
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.o_axi_lite_bvalid (s_bvalid),
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.axi_lite_bvalid (s_bvalid),
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.i_axi_lite_bready (s_bready),
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.axi_lite_bready (s_bready),
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.i_axi_lite_arvalid (s_arvalid),
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.axi_lite_arvalid (s_arvalid),
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.o_axi_lite_arready (s_arready),
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.axi_lite_arready (s_arready),
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.i_axi_lite_araddr (7'd0),
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.axi_lite_araddr (7'd0),
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.o_axi_lite_rvalid (s_rvalid),
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.axi_lite_rvalid (s_rvalid),
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.i_axi_lite_rready (s_rready),
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.axi_lite_rready (s_rready),
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.o_axi_lite_rdata (s_rdata),
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.axi_lite_rdata (s_rdata),
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.o_axi_lite_rresp (s_rresp),
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.axi_lite_rresp (s_rresp),
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// diagnostic output
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// diagnostic output
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.o_diag_addr (s_addr),
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.o_diag_addr (s_addr),
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.o_diag_data (s_data),
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.o_diag_data (s_data),
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.o_diag_wr (s_data_wr),
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.o_diag_wr (s_data_wr),
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// program termination
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// program termination
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