URL https://opencores.org/ocsvn/ssbcc/ssbcc/trunk

Subversion Repositories ssbcc

[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [UART_Rx/] [tb_UART_Rx.9x8-good] - Diff between revs 2 and 9

Rev 2	Rev 9
Line 1...	Line 1...
`# Copyright 2013, Sinclair R.F., Inc.`	`# Copyright 2013, 2015, Sinclair R.F., Inc.`
`# Test bench for UART_Rx peripheral.`	`# Test bench for UART_Rx peripheral.`

`ARCHITECTURE core/9x8 Verilog`	`ARCHITECTURE core/9x8 Verilog`
`INSTRUCTION 64`	`INSTRUCTION 64`
`DATA_STACK 8`	`DATA_STACK 8`
Line 9...	Line 9...
`PARAMETER G_CLK_FREQ_HZ 100_000_000`	`PARAMETER G_CLK_FREQ_HZ 100_000_000`
`PARAMETER G_BAUD 115200`	`PARAMETER G_BAUD 115200`

`PERIPHERAL UART_Rx inport=I_UART_RX \`	`PERIPHERAL UART_Rx inport=I_UART_RX \`
`inempty=I_UART_RX_EMPTY \`	`inempty=I_UART_RX_EMPTY \`
`insignal=i_uart \`	`insignal=i_uart_rx \`
`baudmethod=G_CLK_FREQ_HZ/G_BAUD`	`baudmethod=G_CLK_FREQ_HZ/G_BAUD`

`OUTPORT 8-bit,strobe o_data,o_data_wr O_DATA`	`OUTPORT 8-bit,strobe o_data,o_data_wr O_DATA`

`OUTPORT 1-bit o_done O_DONE`	`OUTPORT 1-bit o_done O_DONE`