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https://opencores.org/ocsvn/ssbcc/ssbcc/trunk
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Line 41... |
wire [7:0] s_diag;
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wire [7:0] s_diag;
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wire s_empty;
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wire s_empty;
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wire s_done;
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wire s_done;
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wire s_diag_rd = ~s_empty && s_readout_en;
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wire s_diag_rd = ~s_empty && s_readout_en;
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reg s_empty_clk = 1'b0;
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tb_outFIFO_async uut(
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tb_outFIFO_async uut(
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// synchronous reset and processor clock
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// synchronous reset and processor clock
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.i_rst (s_rst),
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.i_rst (s_rst),
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.i_clk (s_clk),
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.i_clk (s_clk),
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// asynchronous output FIFO
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// asynchronous output FIFO
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.i_aclk (s_fast_clk),
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.i_aclk (s_fast_clk),
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.o_data (s_diag),
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.o_data (s_diag),
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.i_data_rd (s_diag_rd),
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.i_data_rd (s_diag_rd),
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.o_data_empty (s_empty),
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.o_data_empty (s_empty),
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// feed-back empty condition
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.i_empty (s_empty_clk),
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// termination signal
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// termination signal
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.o_done (s_done)
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.o_done (s_done)
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);
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);
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always @ (posedge s_clk)
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s_empty_clk <= s_empty;
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// validation output
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// validation output
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always @ (posedge s_fast_clk)
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always @ (posedge s_fast_clk)
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if (s_diag_rd)
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if (s_diag_rd)
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$display("%12d : %h", $time, s_diag);
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$display("%12d : %h", $time, s_diag);
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