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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [outFIFO_async/] [tb.v] - Diff between revs 2 and 12

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Rev 2 Rev 12
Line 41... Line 41...
wire      [7:0] s_diag;
wire      [7:0] s_diag;
wire            s_empty;
wire            s_empty;
wire            s_done;
wire            s_done;
 
 
wire            s_diag_rd = ~s_empty && s_readout_en;
wire            s_diag_rd = ~s_empty && s_readout_en;
reg             s_empty_clk = 1'b0;
 
 
 
tb_outFIFO_async uut(
tb_outFIFO_async uut(
  // synchronous reset and processor clock
  // synchronous reset and processor clock
  .i_rst        (s_rst),
  .i_rst        (s_rst),
  .i_clk        (s_clk),
  .i_clk        (s_clk),
  // asynchronous output FIFO
  // asynchronous output FIFO
  .i_aclk       (s_fast_clk),
  .i_aclk       (s_fast_clk),
  .o_data       (s_diag),
  .o_data       (s_diag),
  .i_data_rd    (s_diag_rd),
  .i_data_rd    (s_diag_rd),
  .o_data_empty (s_empty),
  .o_data_empty (s_empty),
  // feed-back empty condition
 
  .i_empty      (s_empty_clk),
 
  // termination signal
  // termination signal
  .o_done       (s_done)
  .o_done       (s_done)
);
);
 
 
always @ (posedge s_clk)
 
  s_empty_clk <= s_empty;
 
 
 
// validation output
// validation output
always @ (posedge s_fast_clk)
always @ (posedge s_fast_clk)
  if (s_diag_rd)
  if (s_diag_rd)
    $display("%12d : %h", $time, s_diag);
    $display("%12d : %h", $time, s_diag);
 
 

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