URL https://opencores.org/ocsvn/ssbcc/ssbcc/trunk

Subversion Repositories ssbcc

[/] [ssbcc/] [trunk/] [core/] [9x8/] [ssbccGenVerilog.py] - Diff between revs 3 and 4

Rev 3	Rev 4
Line 750...	Line 750...
`signalName = signal[0];`	`signalName = signal[0];`
`signalWidth = signal[1];`	`signalWidth = signal[1];`
`signalType = signal[2];`	`signalType = signal[2];`
`signalInit = '%d\'d0' % signalWidth if len(signal)==3 else signal[3];`	`signalInit = '%d\'d0' % signalWidth if len(signal)==3 else signal[3];`
`if signalType == 'data':`	`if signalType == 'data':`
	`fp.write('initial %s = %s;\n' % (signalName,signalInit,));`
`if bitWidth > 0:`	`if bitWidth > 0:`
`bitName += ', ';`	`bitName += ', ';`
`bitInit += ', '`	`bitInit += ', '`
`bitWidth = bitWidth + signalWidth;`	`bitWidth = bitWidth + signalWidth;`
`bitName += signalName;`	`bitName += signalName;`
Line 775...	Line 776...
`signalName = signal[0];`	`signalName = signal[0];`
`signalType = signal[2];`	`signalType = signal[2];`
`if signalType == 'data':`	`if signalType == 'data':`
`pass;`	`pass;`
`elif signalType == 'strobe':`	`elif signalType == 'strobe':`
	`fp.write('initial %s = 1\'b0;\n' % signalName);`
`fp.write('always @ (posedge i_clk)\n');`	`fp.write('always @ (posedge i_clk)\n');`
`fp.write(' if (i_rst)\n');`	`fp.write(' if (i_rst)\n');`
`fp.write(' %s <= 1\'b0;\n' % signalName);`	`fp.write(' %s <= 1\'b0;\n' % signalName);`
`fp.write(' else if (s_outport)\n');`	`fp.write(' else if (s_outport)\n');`
`fp.write(' %s <= (s_T == 8\'h%02X);\n' % (signalName,ix));`	`fp.write(' %s <= (s_T == 8\'h%02X);\n' % (signalName,ix));`