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[/] [ssbcc/] [trunk/] [core/] [9x8/] [ssbccGenVerilog.py] - Diff between revs 3 and 4
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Rev 3 |
Rev 4 |
Line 750... |
Line 750... |
signalName = signal[0];
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signalName = signal[0];
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signalWidth = signal[1];
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signalWidth = signal[1];
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signalType = signal[2];
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signalType = signal[2];
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signalInit = '%d\'d0' % signalWidth if len(signal)==3 else signal[3];
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signalInit = '%d\'d0' % signalWidth if len(signal)==3 else signal[3];
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if signalType == 'data':
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if signalType == 'data':
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fp.write('initial %s = %s;\n' % (signalName,signalInit,));
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if bitWidth > 0:
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if bitWidth > 0:
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bitName += ', ';
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bitName += ', ';
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bitInit += ', '
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bitInit += ', '
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bitWidth = bitWidth + signalWidth;
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bitWidth = bitWidth + signalWidth;
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bitName += signalName;
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bitName += signalName;
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Line 775... |
Line 776... |
signalName = signal[0];
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signalName = signal[0];
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signalType = signal[2];
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signalType = signal[2];
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if signalType == 'data':
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if signalType == 'data':
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pass;
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pass;
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elif signalType == 'strobe':
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elif signalType == 'strobe':
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fp.write('initial %s = 1\'b0;\n' % signalName);
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fp.write('always @ (posedge i_clk)\n');
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fp.write('always @ (posedge i_clk)\n');
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fp.write(' if (i_rst)\n');
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fp.write(' if (i_rst)\n');
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fp.write(' %s <= 1\'b0;\n' % signalName);
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fp.write(' %s <= 1\'b0;\n' % signalName);
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fp.write(' else if (s_outport)\n');
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fp.write(' else if (s_outport)\n');
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fp.write(' %s <= (s_T == 8\'h%02X);\n' % (signalName,ix));
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fp.write(' %s <= (s_T == 8\'h%02X);\n' % (signalName,ix));
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