URL https://opencores.org/ocsvn/ssbcc/ssbcc/trunk

Subversion Repositories ssbcc

[/] [ssbcc/] [trunk/] [core/] [9x8/] [ssbccGenVerilog.py] - Diff between revs 4 and 9

Rev 4	Rev 9
Line 797...	Line 797...
`"""`	`"""`
`if not config.signals:`	`if not config.signals:`
`fp.write('// no additional signals\n');`	`fp.write('// no additional signals\n');`
`return;`	`return;`
`maxLength = 0;`	`maxLength = 0;`
`for ix in range(len(config.signals)):`	`for thisSignal in config.signals:`
`thisSignal = config.signals[ix];`
`signalName = thisSignal[0];`	`signalName = thisSignal[0];`
`if len(signalName) > maxLength:`	`if len(signalName) > maxLength:`
`maxLength = len(signalName);`	`maxLength = len(signalName);`
`maxLength = maxLength + 12;`	`maxLength = maxLength + 12;`
`for ix in range(len(config.signals)):`	`for thisSignal in config.signals:`
`thisSignal = config.signals[ix];`
`signalName = thisSignal[0];`	`signalName = thisSignal[0];`
`signalWidth = thisSignal[1];`	`signalWidth = thisSignal[1];`
`signalInit = "%d'd0" % signalWidth if len(thisSignal) < 3 else thisSignal[2];`	`signalInit = "%d'd0" % signalWidth if len(thisSignal) < 3 else thisSignal[2];`
`outString = 'reg ';`	`outString = 'reg ';`
`if signalWidth == 1:`	`if signalWidth == 1:`