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https://opencores.org/ocsvn/ssbcc/ssbcc/trunk
[/] [ssbcc/] [trunk/] [ssbccUtil.py] - Diff between revs 11 and 12
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| Rev 11 |
Rev 12 |
| Line 68... |
Line 68... |
raise SSBCCException('Malformed range "%s" doesn\'t provide 1 to 8 bits' % bits)
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raise SSBCCException('Malformed range "%s" doesn\'t provide 1 to 8 bits' % bits)
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v /= 2**b0;
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v /= 2**b0;
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v %= 2**bL;
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v %= 2**bL;
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return v;
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return v;
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def InitSignal(nBits,v):
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"""
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Generate an initial value for a Verilog signal.
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"""
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if v == None:
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return None;
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elif type(v) == str:
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return v;
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elif type(v) == int:
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format = '%d\'h%%0%dX' % (nBits,int((nBits+3)/4),);
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return format % v;
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else:
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raise Exception('Program Bug: unrecognized signal type "%s"' % type(signalInit))
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def IntValue(v):
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def IntValue(v):
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"""
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"""
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Convert a Verilog format integer into an integer value.
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Convert a Verilog format integer into an integer value.
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"""
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"""
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save_v = v;
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save_v = v;
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