| Line 43... |
Line 43... |
//
|
//
|
// Create Date: 12:30:30 05/11/2008
|
// Create Date: 12:30:30 05/11/2008
|
// Design Name: Synchronous Serial Peripheral (SSP) Interface UART
|
// Design Name: Synchronous Serial Peripheral (SSP) Interface UART
|
// Module Name: ../VerilogCoponentsLib/SSP_UART/SSP_UART.v
|
// Module Name: ../VerilogCoponentsLib/SSP_UART/SSP_UART.v
|
// Project Name: Verilog Components Library
|
// Project Name: Verilog Components Library
|
// Target Devices: XC3S50A-4VQG100I, XC3S20A-4VQG100I, XC3S700AN-4FFG484I
|
// Target Devices: XC3S50A-4VQG100I, XC3S200A-4VQG100I, XC3S700AN-4FFG484I
|
// Tool versions: ISE 10.1i SP3
|
// Tool versions: ISE 10.1i SP3
|
//
|
//
|
// Description: This module integrates the various elements of a simplified
|
// Description: This module integrates the various elements of a simplified
|
// UART to create a UART that is efficiently supported using a
|
// UART to create a UART that is efficiently supported using a
|
// serial interface. The module also incorporates the logic to
|
// serial interface. The module also incorporates the logic to
|
| Line 90... |
Line 90... |
// function required in the FPGA, increased the FIFO
|
// function required in the FPGA, increased the FIFO
|
// depth of the Tx FIFO to 128 words using distributed
|
// depth of the Tx FIFO to 128 words using distributed
|
// RAM.
|
// RAM.
|
//
|
//
|
// 1.11 08G27 MAM Modified the organization of the SPR window status
|
// 1.11 08G27 MAM Modified the organization of the SPR window status
|
// registers to match Table 5 in the 17000-0403C SSP
|
// registers to match Table 5 in the 1700-0403C SSP
|
// UART specification.
|
// UART specification.
|
//
|
//
|
// 1.20 08G27 MAM Modified Tx signal path to include a FF that will
|
// 1.20 08G27 MAM Modified Tx signal path to include a FF that will
|
// prevent the Tx SM from shifting until the Tx FIFO
|
// prevent the Tx SM from shifting until the Tx FIFO
|
// is loaded with the full message up to the size of
|
// is loaded with the full message up to the size of
|
| Line 187... |
Line 187... |
// (4) RDR - Receive Data Register (3'b011)
|
// (4) RDR - Receive Data Register (3'b011)
|
// (5) SPR - Scratch Pad Register (3'b100)
|
// (5) SPR - Scratch Pad Register (3'b100)
|
//
|
//
|
// The Synchronous Serial Peripheral of the ARM is configured to send 16 bits.
|
// The Synchronous Serial Peripheral of the ARM is configured to send 16 bits.
|
// The result is that the 3 most significant bits are interpreted as an regis-
|
// The result is that the 3 most significant bits are interpreted as an regis-
|
// ter select. Bit 12, the fourth transmitted bit, set the write/read mode of
|
// ter select. Bit 12, the fourth transmitted bit, sets the write/read mode of
|
// transfer. The remaining twelve bits, bits 11...0, are data bits. In this
|
// transfer. The remaining twelve bits, bits 11...0, are data bits. In this
|
// manner, the SSP UART minimizes the number of serial transfers required to
|
// manner, the SSP UART minimizes the number of serial transfers required to
|
// send and receive serial data from the SSP UART. The reads from the TDR/RDR
|
// send and receive serial data from the SSP UART. The reads from the TDR/RDR
|
// addresses also provide status information regarding the transmit and receive
|
// addresses also provide status information regarding the transmit and receive
|
// state machines, and the FIFO-based holding registers. Thus, polling of the
|
// state machines, and the FIFO-based holding registers. Thus, polling of the
|
| Line 240... |
Line 240... |
// Buad Rate Register - BRR (RA = 3'b001) (Write-Only)
|
// Buad Rate Register - BRR (RA = 3'b001) (Write-Only)
|
//
|
//
|
// 11:8 - PS : Baud Rate Prescaler (see table below) - load with (M - 1)
|
// 11:8 - PS : Baud Rate Prescaler (see table below) - load with (M - 1)
|
// 7:0 - Div : Baud Rate Divider (see table below) - load with (N - 1)
|
// 7:0 - Div : Baud Rate Divider (see table below) - load with (N - 1)
|
//
|
//
|
// {PS, Div} : Baud Rate = (Clk / 16) / ((M - 1) * (N - 1))
|
// {PS, Div} : Baud Rate = (Clk / 16) / ((PS + 1) * (Div + 1))
|
//
|
//
|
// Transmit Data Register - TDR (RA = 3'b010)
|
// Transmit Data Register - TDR (RA = 3'b010)
|
//
|
//
|
// 11 - TFC : Transmit FIFO Clear, cleared at end of current cycle
|
// 11 - TFC : Transmit FIFO Clear, cleared at end of current cycle
|
// 10 - RFC : Receive FIFO Clear, cleared at end of current cycle
|
// 10 - RFC : Receive FIFO Clear, cleared at end of current cycle
|
| Line 312... |
Line 312... |
|
|
parameter pRTOChrDlyCnt = 3,
|
parameter pRTOChrDlyCnt = 3,
|
|
|
// FIFO Configuration Parameters
|
// FIFO Configuration Parameters
|
|
|
parameter pTF_Depth = 0, // Tx FIFO Depth: 2**(TF_Depth + 4)
|
parameter pTF_Depth = 2, // Tx FIFO Depth: 2**(TF_Depth + 4)
|
parameter pRF_Depth = 3, // Rx FIFO Depth: 2**(RF_Depth + 4)
|
parameter pRF_Depth = 2, // Rx FIFO Depth: 2**(RF_Depth + 4)
|
parameter pTF_Init = "Src/UART_TF.coe", // Tx FIFO Memory Initialization
|
parameter pTF_Init = "Src/UART_TF.coe", // Tx FIFO Memory Initialization
|
parameter pRF_Init = "Src/UART_RF.coe" // Rx FIFO Memory Initialization
|
parameter pRF_Init = "Src/UART_RF.coe" // Rx FIFO Memory Initialization
|
)(
|
)(
|
input Rst, // System Reset
|
input Rst, // System Reset
|
input Clk, // System Clock
|
input Clk, // System Clock
|
| Line 419... |
Line 419... |
wire RF_FF, RF_EF, RF_HF; // Receive FIFO Flags - Full, Empty, Half
|
wire RF_FF, RF_EF, RF_HF; // Receive FIFO Flags - Full, Empty, Half
|
wire [(pTF_Depth + 4):0] TFCnt; // Tx FIFO Count
|
wire [(pTF_Depth + 4):0] TFCnt; // Tx FIFO Count
|
wire [(pRF_Depth + 4):0] RFCnt; // RX FIFO Count
|
wire [(pRF_Depth + 4):0] RFCnt; // RX FIFO Count
|
|
|
reg [ 7:0] TDR; // Transmit Data Register
|
reg [ 7:0] TDR; // Transmit Data Register
|
// wire [11:0] RDR; // Receive Data Register, UART Status Reg
|
|
reg [11:0] RDR; // Receive Data Register, UART Status Reg
|
reg [11:0] RDR; // Receive Data Register, UART Status Reg
|
reg [11:0] UCR, USR, SPR; // UART Control, Status, & Scratch Pad Regs
|
reg [11:0] UCR, USR, SPR; // UART Control, Status, & Scratch Pad Regs
|
reg [ 7:0] RTFThr; // UART Rx/Tx FIFO Threshold Register
|
reg [ 7:0] RTFThr; // UART Rx/Tx FIFO Threshold Register
|
|
|
wire [1:0] MD; // UCR: Operating Mode
|
wire [1:0] MD; // UCR: Operating Mode
|
