| Line 10... |
Line 10... |
output [1:0] BEN;
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output [1:0] BEN;
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wire nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
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wire nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
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reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
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reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
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reg [5:0] state,nstate;
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reg [5:0] state,nstate;
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reg [2:0] src,dest;
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reg [2:0] src,dest;
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reg RD,cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
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reg WR,RD,cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
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wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq,pc_sh;
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wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq,pc_sh;
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wire [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
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wire [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
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wire [32:0] adder_out,sub_out;
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wire [32:0] adder_out,sub_out;
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wire [4:0] EBX_shtr;
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wire [4:0] EBX_shtr;
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wire signed [31:0] ssregsrc, ssregdest;
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wire signed [31:0] ssregsrc, ssregdest;
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| Line 126... |
Line 126... |
`sdv3 : if (nbF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
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`sdv3 : if (nbF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
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`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
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`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
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default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
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default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
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endcase
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endcase
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case(state) // ESP control
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case(state) // ESP control
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`init : ESP <= 32'h01f1fc;
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`init : ESP <= 32'h03b1fc;
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`call,`calla: ESP <= ESP - 4'b0100;
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`call,`calla: ESP <= ESP - 4'b0100;
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`ret2 : ESP <= ESP + 4'b0100;
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`ret2 : ESP <= ESP + 4'b0100;
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default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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endcase
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endcase
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
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case(state) // PC control
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case(state) // PC control
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`init : PC<=32'h00;
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`init : PC<=32'h0020000;
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`jae2 : PC<=pc_jae;
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`jae2 : PC<=pc_jae;
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`jbe2 : PC<=pc_jbe;
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`jbe2 : PC<=pc_jbe;
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`ja2 : PC<=pc_ja ;
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`ja2 : PC<=pc_ja ;
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`jb2 : PC<=pc_jb ;
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`jb2 : PC<=pc_jb ;
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`jge2 : PC<=pc_jge;
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`jge2 : PC<=pc_jge;
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| Line 194... |
Line 194... |
6'b001010 : {ncry,alu_out} = sub_out ; // SUB , carry generation
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6'b001010 : {ncry,alu_out} = sub_out ; // SUB , carry generation
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6'b001100 : {ncry,alu_out} = {cry,regdest ^ regsrc}; // XOR
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6'b001100 : {ncry,alu_out} = {cry,regdest ^ regsrc}; // XOR
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6'b100010 : {ncry,alu_out} = {cry, regsrc}; // MOVE
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6'b100010 : {ncry,alu_out} = {cry, regsrc}; // MOVE
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6'b101101 : {ncry,alu_out} = {cry, Zregsrc}; // MOVE
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6'b101101 : {ncry,alu_out} = {cry, Zregsrc}; // MOVE
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6'b101111 : {ncry,alu_out} = {cry, Sregsrc}; // MOVE
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6'b101111 : {ncry,alu_out} = {cry, Sregsrc}; // MOVE
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//6'b110000 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
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//6'b110100 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
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default : {ncry,alu_out} = {cry,regdest }; // DO NOTHING
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default : {ncry,alu_out} = {cry,regdest }; // DO NOTHING
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endcase
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endcase
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else if (state == `shift ) {ncry,alu_out} = {cry,sft_out };
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else if (state == `shift ) {ncry,alu_out} = {cry,sft_out };
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else {ncry,alu_out} = {cry,regdest };
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else {ncry,alu_out} = {cry,regdest };
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// Main instruction decode
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// Main instruction decode
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always @(ID,state,ECX,EBX_shtr,EAX,divF1,divF2)
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always @(ID,state,ECX,EBX_shtr,EAX,divF1,divF2)
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begin
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begin
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// One cycle instructions, operand selection
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// One cycle instructions, operand selection
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if ((state == `fetch) || (state ==`shift))
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if ((state == `fetch) || (state ==`shift))
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casex ({ID[15:14],ID[13],ID[9],ID[7]})
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casex ({ID[15:12],ID[10:9],ID[7]})
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5'b10x00 : begin RD=0; src=ID[5:3]; dest= 3'b111; end // store into ram (x89 x00)
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7'b10x0000 : begin RD=0;WR=1; src=ID[5:3]; dest= 3'b111; end // store into ram (x89 x00)
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5'b10010 : begin RD=1; src= 3'b111; dest=ID[5:3]; end // load from ram (x8b x00)
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7'b100xx10 : begin RD=1;WR=0; src= 3'b111; dest=ID[5:3]; end // load from ram (x8b x00)
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5'b10110 : begin RD=0; src= 3'b111; dest=ID[5:3]; end // load bl with immediate
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7'b101xx10 : begin RD=0;WR=0; src= 3'b111; dest=ID[5:3]; end // load bl with immediate
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5'b10x11 : begin RD=0; src=ID[2:0]; dest=ID[5:3]; end // reg2reg xfer (x8b xC0)
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7'b10xxx11 : begin RD=0;WR=0; src=ID[2:0]; dest=ID[5:3]; end // reg2reg xfer (x8b xC0)
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5'b00x11 : begin RD=0; src=ID[2:0]; dest=ID[5:3]; end // alu op
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7'b00xxx11 : begin RD=0;WR=0; src=ID[2:0]; dest=ID[5:3]; end // alu op
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default : begin RD=0; src=ID[5:3]; dest=ID[2:0]; end // shift
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default : begin RD=0;WR=0; src=ID[5:3]; dest=ID[2:0]; end // shift
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endcase
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endcase
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else if (state==`ret)
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else if (state==`ret)
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begin src = 3'b011; dest = 3'b100; RD=0; end
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begin src = 3'b011; dest = 3'b100; RD=0; WR=0; end
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else if (state==`sdv3)
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else if (state==`sdv3)
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begin src = 3'b001; dest = 3'b010; RD=0; end
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begin src = 3'b001; dest = 3'b010; RD=0; WR=0; end
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else begin src = 3'b000; dest = 3'b000; RD=0; end
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else begin src = 3'b000; dest = 3'b000; RD=0; WR=0; end
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// instructions that require more than one cycle to execute
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// instructions that require more than one cycle to execute
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if (state == `fetch)
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if (state == `fetch)
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begin
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begin
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casex(ID)
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casex(ID)
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16'h90e9: nstate = `jmp;
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16'h90e9: nstate = `jmp;
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| Line 290... |
Line 288... |
end
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end
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end
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end
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assign ssregsrc = regsrc;
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assign ssregsrc = regsrc;
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assign ssregdest= regdest;
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assign ssregdest= regdest;
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assign IA = PC ;
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assign IA = PC ;
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assign A =((state == `call2)|(state == `calla2)) ? ESP : EBX ;
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assign A =((state == `call2)|(state == `calla2)|((WR==1)&(ID[2:0]==3'b100))) ? ESP : EBX ;
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assign Q =((state == `call2)|(state == `calla2)) ? incPC : regsrc ;
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assign Q =((state == `call2)|(state == `calla2)) ? incPC : regsrc ;
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assign WEN = (CE == 1'b0) ? 1'b1 :
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assign WEN = (CE == 1'b0) ? 1'b1 :
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({ID[15:9],ID[7]}==8'h88)? 1'b0 :
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(WR == 1'b1) ? 1'b0 :
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(state == `call2) ? 1'b0 :
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(state == `call2) ? 1'b0 :
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(state == `calla2)? 1'b0 : 1'b1 ;
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(state == `calla2)? 1'b0 : 1'b1 ;
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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{ {24{regsrc[7] }} , regsrc[7:0] } ;
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{ {24{regsrc[7] }} , regsrc[7:0] } ;
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assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
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assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
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{ 24'b0 , regsrc[7:0] } ;
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{ 24'b0 , regsrc[7:0] } ;
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assign BEN =((state == `call2)|(state == `calla2)) ? 1'b1 : { prefx , ID[8] } ;
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assign BEN =((state == `call2)|(state == `calla2)) ? 1'b1 : { prefx , ID[8] } ;
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assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
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assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
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assign nbF = (regsrc > regdest) ? 1'b1 : 1'b0;
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assign nbF = (regsrc > regdest) ? 1'b1 : 1'b0;
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assign naF = ~(nlF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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assign naF = ~(nlF | neqF );
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assign nlF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;
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assign nlF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;
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assign ngF = ~(nbF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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assign ngF = ~(nbF | neqF );
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assign incPC = PC + 3'b010;
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assign incPC = PC + 3'b010;
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assign pc_jge = (eqF|gF) ? pc_jp : incPC;
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assign pc_jge = (eqF|gF) ? pc_jp : incPC;
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assign pc_jle = (eqF|lF) ? pc_jp : incPC;
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assign pc_jle = (eqF|lF) ? pc_jp : incPC;
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assign pc_jg = (gF ) ? pc_jp : incPC;
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assign pc_jg = (gF ) ? pc_jp : incPC;
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assign pc_jl = (lF ) ? pc_jp : incPC;
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assign pc_jl = (lF ) ? pc_jp : incPC;
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