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module sub86( CLK, RSTN, IA, ID, A, D, Q, WEN,BEN,CE,RD );
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module sub86( CLK, RSTN, IA, ID, A, D, Q, WEN,BEN,CE,RD,INT );
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input CLK,RSTN,CE;
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input CLK,RSTN,CE,INT;
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output [31:0] IA;
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input [15:0] ID;
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input [15:0] ID;
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output [31:0] A;
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input [31:0] D;
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input [31:0] D;
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output [31:0] IA;
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output [31:0] A;
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output [31:0] Q;
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output [31:0] Q;
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output WEN;
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output WEN,RD;
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output RD;
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output [1:0] BEN;
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output [1:0] BEN;
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wire nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
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reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
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reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
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reg [5:0] state,nstate;
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reg [5:0] state,nstate;
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reg [2:0] src,dest;
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reg [2:0] src,dest;
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reg WR,RD,cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
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reg WR,RD,cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
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wire nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
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wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq,pc_sh;
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wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq,pc_sh;
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wire [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
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wire [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
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wire [32:0] adder_out,sub_out;
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wire [32:0] adder_out,sub_out;
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wire [4:0] EBX_shtr;
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wire [4:0] EBX_shtr;
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wire signed [31:0] ssregsrc, ssregdest;
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wire signed [31:0] ssregsrc, ssregdest;
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end
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end
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end
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end
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assign ssregsrc = regsrc;
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assign ssregsrc = regsrc;
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assign ssregdest= regdest;
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assign ssregdest= regdest;
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assign IA = PC ;
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assign IA = PC ;
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assign A =((state == `call2)|(state == `calla2)|((WR==1)&(ID[2:0]==3'b100))) ? ESP : EBX ;
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assign A =((state == `call2)|(state == `calla2)) ? ESP : EBX ;
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assign Q =((state == `call2)|(state == `calla2)) ? incPC : regsrc ;
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assign Q =((state == `call2)|(state == `calla2)) ? incPC : regsrc ;
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assign WEN = (CE == 1'b0) ? 1'b1 :
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assign WEN = (CE == 1'b0) ? 1'b1 :
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(WR == 1'b1) ? 1'b0 :
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(WR == 1'b1) ? 1'b0 :
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(state == `call2) ? 1'b0 :
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(state == `call2) ? 1'b0 :
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(state == `calla2)? 1'b0 : 1'b1 ;
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(state == `calla2)? 1'b0 : 1'b1 ;
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