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[/] [sub86/] [trunk/] [sub86.v] - Diff between revs 11 and 12

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Rev 11 Rev 12
Line 8... Line 8...
output        WEN,RD;
output        WEN,RD;
output  [1:0] BEN;
output  [1:0] BEN;
reg    [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
reg    [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
reg     [5:0] state,nstate;
reg     [5:0] state,nstate;
reg     [2:0] src,dest;
reg     [2:0] src,dest;
reg           WR,RD,cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
reg           INTreg,WR,RD,cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
wire          nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
wire          INTvalid,nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
wire   [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq,pc_sh;
wire   [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq,pc_sh;
wire   [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
wire   [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
wire   [32:0] adder_out,sub_out;
wire   [32:0] adder_out,sub_out;
wire    [4:0] EBX_shtr;
wire    [4:0] EBX_shtr;
wire signed [31:0] ssregsrc, ssregdest;
wire signed [31:0] ssregsrc, ssregdest;
Line 63... Line 63...
`define div1  6'b101100
`define div1  6'b101100
`define leas  6'b101101
`define leas  6'b101101
`define calla 6'b101110
`define calla 6'b101110
`define calla2 6'b101111
`define calla2 6'b101111
`define shft3 6'b110000
`define shft3 6'b110000
 
`define int1  6'b110001
 
`define int2  6'b110010
`define init  6'b000000
`define init  6'b000000
 
 
 always @(posedge CLK)
 always @(posedge CLK)
 
      casex ({RSTN,INT,((RD|WR)&CE)}) // interrupt control
 
        3'b0xx   : INTreg <= 1'b0;
 
        3'b11x   : INTreg <= 1'b1;
 
        3'b1x1   : INTreg <= 1'b0;
 
        default  : INTreg <= INTreg;
 
      endcase
 
 
 
 always @(posedge CLK)
   if ((CE ==1'b1) || (RSTN ==1'b0))
   if ((CE ==1'b1) || (RSTN ==1'b0))
     begin
     begin
      case (state) // cry control
      case (state) // cry control
         `sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
         `sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
         `div1      : cry <= 1'b0;
         `div1      : cry <= 1'b0;
Line 125... Line 135...
        `sdv3       : if (nbF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
        `sdv3       : if (nbF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
        `sdv4       : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
        `sdv4       : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
        default     : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
        default     : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
      endcase
      endcase
      case(state)  // ESP control
      case(state)  // ESP control
        `init        : ESP <= 32'h03b1fc;
        `init              : ESP <= 32'h0161fc;
        `call,`calla : ESP <= ESP - 4'b0100;
        `call,`calla,`int1 : ESP <= ESP - 4'b0100;
        `ret2        : ESP <= ESP + 4'b0100;
        `ret2        : ESP <= ESP + 4'b0100;
       default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
       default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
      endcase
      endcase
      if (dest==3'b101) EBP <= alu_out; else EBP<=EBP;  // EBP control 
      if (dest==3'b101) EBP <= alu_out; else EBP<=EBP;  // EBP control 
      case(state)  // PC control
      case(state)  // PC control
       `init        : PC<=32'h0020000;
       `init        : PC<=32'h0001000;
 
       `int2        : PC<=32'h0;
       `jae2        : PC<=pc_jae;
       `jae2        : PC<=pc_jae;
       `jbe2        : PC<=pc_jbe;
       `jbe2        : PC<=pc_jbe;
       `ja2         : PC<=pc_ja ;
       `ja2         : PC<=pc_ja ;
       `jb2         : PC<=pc_jb ;
       `jb2         : PC<=pc_jb ;
       `jge2        : PC<=pc_jge;
       `jge2        : PC<=pc_jge;
Line 147... Line 158...
       `jne2        : PC<=pc_neq;
       `jne2        : PC<=pc_neq;
       `jmp2,`call2 : PC<=pc_jp ;
       `jmp2,`call2 : PC<=pc_jp ;
       `calla2      : PC<=EBX;
       `calla2      : PC<=EBX;
       `ret2        : PC<=D     ;
       `ret2        : PC<=D     ;
       `mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
       `mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
       `shift       : PC<=PC    ;
       `shift,`int1 : PC<=PC    ;
       default      : if (nstate == `shift) PC<=PC;
       `fetch       : if (nstate == `shift) PC<=PC;
                 else if (ID[15:8]==8'heb) PC <= pc_sh;
                 else if (ID[15:8]==8'heb) PC <= pc_sh;
                 else if((ID[15:8]==8'h75) && (eqF==1'b0)) PC <= pc_sh;
                 else if((ID[15:8]==8'h75) && (eqF==1'b0)) PC <= pc_sh;
                 else if((ID[15:8]==8'h74) && (eqF==1'b1)) PC <= pc_sh;
                 else if((ID[15:8]==8'h74) && (eqF==1'b1)) PC <= pc_sh;
                 else PC<=incPC ;
                 else PC<=incPC ;
 
       default      : PC<=incPC ;
      endcase
      endcase
     end
     end
// muxing for source selection, used in alu & moves
// muxing for source selection, used in alu & moves
always@(src,EAX,ECX,EDX,EBX,ESP,EBP,D)
always@(src,EAX,ECX,EDX,EBX,ESP,EBP,D)
   case(src)
   case(src)
Line 198... Line 210...
   default   : {ncry,alu_out} = {cry,regdest         };  // DO NOTHING
   default   : {ncry,alu_out} = {cry,regdest         };  // DO NOTHING
  endcase
  endcase
  else if (state == `shift ) {ncry,alu_out} = {cry,sft_out           };
  else if (state == `shift ) {ncry,alu_out} = {cry,sft_out           };
  else {ncry,alu_out} = {cry,regdest         };
  else {ncry,alu_out} = {cry,regdest         };
// Main instruction decode
// Main instruction decode
always @(ID,state,ECX,EBX_shtr,EAX,divF1,divF2)
always @(ID,state,ECX,EBX_shtr,EAX,divF1,divF2,INTvalid)
 begin
 begin
   // One cycle instructions, operand selection
   // One cycle instructions, operand selection
   if ((state == `fetch) || (state ==`shift))
   if ((state == `fetch) || (state ==`shift))
     casex ({ID[15:12],ID[10:9],ID[7]})
     casex ({ID[15:12],ID[10:9],ID[7]})
      7'b10x0000  : begin RD=0;WR=1; src=ID[5:3]; dest= 3'b111; end  // store into ram (x89 x00)
      7'b10x0000  : begin RD=0;WR=1; src=ID[5:3]; dest= 3'b111; end  // store into ram (x89 x00)
Line 218... Line 230...
        begin src = 3'b001; dest = 3'b010; RD=0; WR=0; end
        begin src = 3'b001; dest = 3'b010; RD=0; WR=0; end
   else begin src = 3'b000; dest = 3'b000; RD=0; WR=0; end
   else begin src = 3'b000; dest = 3'b000; RD=0; WR=0; end
   // instructions that require more than one cycle to execute
   // instructions that require more than one cycle to execute
   if (state == `fetch)
   if (state == `fetch)
   begin
   begin
    casex(ID)
     casex({INTvalid,ID})
     16'h90e9: nstate = `jmp;
     17'h1xxxx: nstate = `int1;
     16'h0f87: nstate = `ja;
     17'h090e9: nstate = `jmp;
     16'h0f86: nstate = `jbe;
     17'h00f87: nstate = `ja;
     16'h0f83: nstate = `jae;
     17'h00f86: nstate = `jbe;
     16'h0f82: nstate = `jb;
     17'h00f83: nstate = `jae;
     16'h0f8f: nstate = `jg;
     17'h00f82: nstate = `jb;
     16'h0f8e: nstate = `jle;
     17'h00f8f: nstate = `jg;
     16'h0f8d: nstate = `jge;
     17'h00f8e: nstate = `jle;
     16'h0f8c: nstate = `jl;
     17'h00f8d: nstate = `jge;
     16'h0f85: nstate = `jne;
     17'h00f8c: nstate = `jl;
     16'h0f84: nstate = `je;
     17'h00f85: nstate = `jne;
     16'h90bb: nstate = `imm;
     17'h00f84: nstate = `je;
     16'h8d9d: nstate = `lea;
     17'h090bb: nstate = `imm;
     16'h8d5d: nstate = `leas;
     17'h08d9d: nstate = `lea;
     16'h90e8: nstate = `call;
     17'h08d5d: nstate = `leas;
     16'h90c3: nstate = `ret;
     17'h090e8: nstate = `call;
     16'hc1xx: nstate = `shift;
     17'h090c3: nstate = `ret;
     16'hd3xx: nstate = `shift;
     17'h0c1xx: nstate = `shift;
     16'hf7e1: nstate = `mul;
     17'h0d3xx: nstate = `shift;
     16'hf7f9: nstate = `sdv1;
     17'h0f7e1: nstate = `mul;
     16'hf7f1: nstate = `div1;
     17'h0f7f9: nstate = `sdv1;
     16'hafc1: nstate = `sml1;
     17'h0f7f1: nstate = `div1;
     16'hffd3: nstate = `calla;
     17'h0afc1: nstate = `sml1;
 
     17'h0ffd3: nstate = `calla;
     default : nstate = `fetch;
     default : nstate = `fetch;
    endcase
    endcase
    if (ID       == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
    if (ID       == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
    if (ID[15:8] ==  8'h39  ) cmpr   = 1'b1; else cmpr   = 1'b0;
    if (ID[15:8] ==  8'h39  ) cmpr   = 1'b1; else cmpr   = 1'b0;
   end
   end
   else
   else
   begin
   begin
        nprefx = 1'b0; cmpr   = 1'b0;
        nprefx = 1'b0; cmpr   = 1'b0;
        if((state==`mul)&&!(ECX==32'b0)) nstate=`mul;
        if (state==`int1)  nstate = `int2;
 
   else if((state==`mul)&&!(ECX==32'b0)) nstate=`mul;
   else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
   else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
   else if (state==`mul2)  nstate = `fetch;
   else if (state==`mul2)  nstate = `fetch;
   else if (state==`sml1)  nstate = `sml2;
   else if (state==`sml1)  nstate = `sml2;
   else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
   else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
   else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
   else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
Line 284... Line 298...
   else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
   else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
   else if (state==`shft2) nstate = `shft3;
   else if (state==`shft2) nstate = `shft3;
   else                    nstate = `fetch;
   else                    nstate = `fetch;
   end
   end
 end
 end
 
assign INTvalid = INTreg & (WR | RD);
assign ssregsrc = regsrc;
assign ssregsrc = regsrc;
assign ssregdest= regdest;
assign ssregdest= regdest;
assign  IA      = PC                ;
assign  IA      = PC                ;
assign  A       =((state == `call2)|(state == `calla2)) ?  ESP          : EBX      ;
assign  A       =((state == `call2)|(state == `calla2)|(state == `int2)) ?  ESP          : EBX      ;
assign  Q       =((state == `call2)|(state == `calla2)) ?  incPC        : regsrc   ;
assign  Q       =((state == `call2)|(state == `calla2)|(state == `int2)) ?  incPC        : regsrc   ;
assign  WEN     = (CE    ==   1'b0) ?  1'b1         :
assign  WEN     = (CE    ==   1'b0) ?  1'b1         :
                  (WR    ==   1'b1) ?  1'b0         :
                  (WR    ==   1'b1) ?  1'b0         :
                  (state == `call2) ?  1'b0         :
                  (state == `call2) ?  1'b0         :
 
                  (state == `int2 ) ?  1'b0         :
                  (state == `calla2)?  1'b0         : 1'b1     ;
                  (state == `calla2)?  1'b0         : 1'b1     ;
assign  Sregsrc =       ID[8]       ? { {16{regsrc[15]}} , regsrc[15:0] } :
assign  Sregsrc =       ID[8]       ? { {16{regsrc[15]}} , regsrc[15:0] } :
                                      { {24{regsrc[7] }} , regsrc[7:0]  } ;
                                      { {24{regsrc[7] }} , regsrc[7:0]  } ;
assign  Zregsrc =       ID[8]       ? {  16'b0           , regsrc[15:0] } :
assign  Zregsrc =       ID[8]       ? {  16'b0           , regsrc[15:0] } :
                                      {  24'b0           , regsrc[7:0]  } ;
                                      {  24'b0           , regsrc[7:0]  } ;

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